System and method for common mode calibration in an analog to digital converter

1. A conversion circuit, comprising;

a front-end circuit creating an analog-to-digital converter (ADC) input voltage having a input common mode voltage; and

an ADC coupled to said front-end circuit;

wherein a calibration voltage having a calibration common mode voltage is input to said ADC for comparison to said ADC input voltage and said front-end circuit is adjusted so said input common mode voltage substantially equals said calibration common mode voltage.

2. The conversion circuit of claim 1 , wherein said front-end circuit comprises a track-and-hold circuit having a hold mode and a track mode, wherein said input common mode voltage is adjusted only during one of said hold mode or said track mode.

3. The conversion circuit of claim 1 , further comprising:

a feedback controller circuit; and

a common mode reference voltage circuit having an output and an input, wherein said common mode reference voltage circuit input is coupled to an ADC output via said feedback controller circuit;

wherein said common mode reference voltage circuit output is coupled to said front-end circuit.

4. The conversion circuit of claim 3 , wherein said feedback controller circuit further comprises:

an integrator having an input and an output, wherein said integrator input is coupled to said ADC output;

a flip-flop having an input and an output, wherein said flip-flop output is coupled to said common mode reference voltage circuit input; and

a summation circuit having an additive input coupled to said integrator output, a subtractive input coupled to said flip-flop output, and an output coupled to said flip-flop input.

5. The conversion circuit of claim 4 , wherein said integrator further comprises:

an amplifier having an input and an output, wherein said amplifier input is coupled between said ADC output and said first flip-flop input;

a second flip-flop having an input, an output, and a reset input;

an overflow circuit having an input coupled to said second flip-flop output, an output coupled to said summation circuit additive input, and a reset output coupled to said second flip-flop reset input; and

a second summation circuit having an additive input coupled to said amplifier output, a subtractive input coupled to said second flip-flop output, and an output coupled to said second flip-flop input.

6. The conversion circuit of claim 3 , wherein said feedback controller circuit further comprises a low pass filter.

7. The conversion circuit of claim 6 , wherein said switching circuit includes a multiplexer.

8. The conversion circuit of claim 6 , further comprising a calibration voltage circuit coupled to said switching circuit.

9. The conversion circuit of claim 1 , further comprising a switching circuit coupled between said front-end circuit and said ADC.

10. The conversion circuit of claim 1 , wherein said conversion circuit is deposited on a substrate.

11. A method for common mode calibration, comprising:

comparing an analog-to-digital converter input signal to a reference voltage to determine a common mode offset voltage; and

minimizing said common mode offset voltage to calibrate said analog-to-digital converter input signal.

12. The method of claim 11 , wherein a track-and-hold circuit provides said analog-to-digital converter input signal and at least one of said comparing and said minimizing occurs during a hold mode of said track-and-hold circuit.

13. The method of claim 11 , wherein said reference voltage is a calibration common mode voltage, said analog-to-digital converter input signal has an input common mode voltage, and said comparing determines a difference between said calibration common mode voltage and said input common mode voltage.

14. The method of claim 11 , wherein said comparing is performed with an analog-to-digital converter.

15. The method of claim 11 , wherein said minimizing reduces said common mode offset voltage to substantially zero volts.

16. The method of claim 11 , wherein said minimizing further includes adjusting a front-end circuit.

17. The method of claim 16 , wherein said adjusting further includes varying a voltage input to said front-end circuit.

18. The method of claim 11 , wherein said minimizing is controlled by measuring an analog-to-digital converter output and adjusting a front-end circuit with a feedback controller circuit.

19. A method for increasing an analog to digital converter (ADC) input preamplifier gain in an ADC input preamplifier, comprising:

comparing an ADC input signal to a calibration reference voltage to determine a common mode offset voltage; and

adjusting an ADC input common mode voltage to minimize said common mode offset voltage,

wherein said adjusting increases the ADC input preamplifier gain.

20. The method of claim 19 , wherein at least one of said comparing and said adjusting occurs during a hold mode of the track-and-hold circuit or a track mode of the track-and-hold circuit.

21. The method of claim 19 , wherein said comparing further comprises using an analog-to-digital converter to perform said comparing.

22. The method of claim 19 , wherein said adjusting reduces said common mode offset voltage to substantially zero volts.

23. The method of claim 19 , wherein said adjusting includes using a variable front-end circuit.

24. The method of claim 23 , wherein said adjusting further includes varying a voltage input to said front-end circuit.

25. The method of claim 19 , wherein said adjusting includes measuring an analog-to-digital converter output and varying a front-end circuit with a feedback controller circuit.