NAND memory with virtual channel
View Patent ↗A string of nonvolatile memory cells are connected together by source/drain regions that include an inversion layer created by fixed charge in an overlying layer. Control gates extend between floating gates so that two control gates couple to a floating gate. A fixed charge layer may be formed by plasma nitridation.
1. A nonvolatile memory array comprising:
a plurality of floating gate memory cells connected together in series, the plurality of floating gate memory cells electrically connected by source/drain regions, a source/drain region including an inversion layer that results from a fixed electrical charge within a fixed charge layer portion that extends over the source/drain region, a tunnel oxide underlying the plurality of floating gates, control gates extending between floating gates such that a control gate overlies the fixed charge layer portion.
2. The nonvolatile memory array of claim 1 wherein the fixed charge layer portion is a nitrided Silicon Dioxide.
3. The nonvolatile memory array of claim 1 wherein the plurality of floating gate memory cells is a NAND string.
4. The nonvolatile memory array of claim 1 wherein each of the plurality of floating gate memory cells has an inverted-T shape in cross section.
5. The nonvolatile memory array of claim 1 further comprising an interlayer dielectric layer extending between floating gates and control gates.
6. A nonvolatile memory array comprising:
a NAND string comprising a plurality of memory cells connected in series, each of the plurality of memory cells having a floating gate;
a plurality of control gates, each of the plurality of control gates extending between adjacent floating gates;
a plurality of source/drain regions that electrically connect the plurality of memory cells in series, each of the plurality of source/drain regions underlying one of the plurality of control gates; and
a plurality of fixed charge layer portions, each of the plurality of fixed charge layer portions extending over one of the plurality of source/drain regions, each of the plurality of fixed charge layer portions holding a fixed electrical charge, the source/drain regions result from the fixed charge layer portions.
7. The nonvolatile memory array of claim 6 further comprising select gates at either end of the NAND string.
8. The nonvolatile memory array of claim 6 wherein the fixed charge layer portions are nitrided Silicon Dioxide.
9. The nonvolatile memory array of claim 6 wherein each floating gate is coupled to two control gates.
10. A nonvolatile memory array comprising:
a plurality of floating gate memory cells connected together in series, the plurality of floating gate memory cells electrically connected by source/drain regions, a source/drain region results from a fixed electrical charge within a fixed charge layer portion that extends over the source/drain region, control gates extending between floating gates such that a control gate overlies the fixed charge layer portion.
11. The nonvolatile memory array of claim 10 , wherein the fixed charge layer portion is a nitrided silicon dioxide.
12. The nonvolatile memory array of claim 10 , wherein the plurality of floating gate memory cells is a NAND string.