Nanowire semiconductor device
View Patent ↗Semiconductor devices may be fabricated using nanowires. In an example embodiment, a conductive gate may be used to control conduction along the nanowires, in which case one of the contacts is a drain and the other a source. The nanowires may be grown in a trench or through-hole in a substrate or in particular in an epitaxial layer on substrate. In another example embodiment, the gate may be provided only at one end of the nanowires. The nanowires can be of the same material along their length; alternatively different materials can be used, especially different materials adjacent to the gate and between the gate and the base of the trench.
1. A semiconductor device comprising:
a substrate defining opposed first and second major surfaces;
at least one conductive nanowire extending substantially perpendicularly to the major surfaces ( 4 ) defining a body region ( 29 ) and a drift region ( 28 ) along the length of the nanowire ( 16 );
a gate region of conductive material insulated from the nanowires ( 16 ) and arranged adjacent to the body region ( 29 ) of the nanowires ( 16 ) and spaced from the drift region ( 28 ) end of the nanowires ( 16 ) to control conduction in the nanowires in the body region ( 29 ) of the nanowires.
2. A semiconductor device according claim 1 wherein the nanowire or nanowires are embedded in dielectric material.
3. A semiconductor device according to claim 1 wherein the nanowires are formed of a first material in the body region adjacent to the gate and a different second material in the drift region not adjacent to the gate.
4. A semiconductor device according to claim 3 wherein the second material has a higher maximum electric field strength before breakdown than the first material.
5. A semiconductor device according to claim 1 comprising at least one trench extending from the first major surface ( 4 ) towards the second major surface, the nanowires extending in the trench.
6. A semiconductor device according to claim 5 further comprising a dielectric layer on the sidewalls of the at least one trench a dielectric layer on the surface of the substrate, wherein the conductive gate region is formed on the dielectric layer on the surface of the substrate.
7. A semiconductor device according to claim 5 wherein a plurality of nanowires are provided in the or each trench.
8. A semiconductor device according to claim 5 wherein a single nanowire fills the or each trench.
9. A semiconductor device according to claim 5 wherein the substrate is silicon.
10. A semiconductor device according to claim 5 wherein the substrate is of aluminium oxide.
11. A semiconductor device comprising:
a substrate defining opposed first and second major surfaces
at least one conductive nanowire extending substantially perpendicularly to the major surfaces defining a first region and a second region along the length of the nanowire
wherein the nanowires are formed of a first material in the first region and a different second material in the second region.
12. A semiconductor device comprising:
a semiconductor substrate having opposed first and second major surfaces
at least one trench extending from the first major surface of the substrate through the semiconductor substrate
insulator on the sidewalls of the trench;
a first contact at the first major surface of the substrate and
at least one conductive nanowire extending from the first contact to the base of the trench through the trench.
13. A semiconductor device according to claim 12 further comprising a gate for controlling conduction in the at least one nanowire through the trench.
14. A semiconductor device according to claim 12 wherein a plurality of conductive nanowires are provided in each trench.
15. A semiconductor device according to claim 12 wherein the substrate is silicon.
16. A semiconductor device comprising:
a substrate defining opposed first and second major surfaces
a gate;
a plurality of conductive nanowires extending substantially perpendicularly to the major surfaces through the gate; and
a gate dielectric on each nanowire electrically isolating the gate from the respective nanowire.
17. A semiconductor device according to claim 16 wherein the substrate is a metal plate.