Fully siliciding regions to improve performance
View Patent ↗Structures and related methods including fully silicided regions are disclosed. In one embodiment, a structure includes a substrate; a partially silicided region located in an active region of an integrated circuit formed on the substrate; a fully silicided region located in a non-active region of the integrated circuit, and wherein the partially and fully silicided regions are formed from a common semiconductor layer.
1. A structure comprising:
a substrate;
a partially silicided region located in an active region of an integrated circuit formed on the substrate, wherein the partially silicided region is located in a source/drain region of a first field effect transistor (FET) and a source/drain region of a second field effect transistor (FET);
a fully silicided region located in a non-active region of the integrated circuit, wherein the fully silicided region is located in an interconnect region between the first FET and the second FET, the fully silicided region interconnecting the partially silicided region located in the source/drain region of the first FET and the source/drain region of the second FET; and
wherein the partially and fully silicided regions are formed from a common semiconductor layer.
2. The structure of claim 1 , wherein the fully silicided region includes a butted junction located between the source/drain regions of the first FET and the second FET.
3. The structure of claim 2 , wherein one of the first and second FETs is a pFET and the other is an nFET.
4. The structure of claim 1 , wherein the partially silicided region includes a gate conductor.
5. The structure of claim 1 , wherein the interconnect region couples partially silicided gate conductors.
6. A structure comprising:
a substrate;
a first field effect transistor (FET) on the substrate;
a second field effect transistor (FET) on the substrate;
a partially silicided region located in a source/drain region of the first FET and a source/drain region of the second FET: and
a fully silicided region positioned in the substrate in an interconnect region between the first FET and the second FET, the fully silicided region interconnecting the partially silicided region located in the source/drain region of the first FET and the source/drain region of the second FET, the fully silicided region acting as an isolation region between active regions of the first FET and second FET.
7. The structure of claim 6 , wherein one of the first and second FETs is a pFET and the other is an nFET.
8. The structure of claim 6 , wherein each of the first and second FET is an nFET.
9. The structure of claim 8 , wherein the fully silicided region interconnects acts as an interconnect between active regions of the first and second FET.
10. The structure of claim 6 , further comprising a fully silicided wiring region adjacent to the first and second FET.
11. A method comprising:
forming a polysilicon layer over at least one active silicon region in a dielectric layer;
partially siliciding a first region of the polysilicon layer over the at least one active silicon region;
fully siliciding a second region of the polysilicon layer over a non-active silicon region; and
wherein the fully silicided second region interconnects with the partially silicided first region.
12. The method of claim 11 , wherein the fully silicided second region includes a gate conductor.
13. The method of claim 11 , wherein the fully silicided second region includes a region between active regions of a pair of field effect transistors.
14. The method of claim 11 , wherein the fully silicided second region includes a wiring region.
15. The method of claim 11 wherein the partially silicided first region includes a gate conductor.