Method and apparatus for affecting a portion of an integrated circuit

1. A method for testing a first module and a second module on a same integrated circuit, the method comprising:

assigning the first module to be tested,

wherein the first module has a first state machine,

wherein the first state machine is compatible with an IEEE 1149.1 standard, and

wherein a transition of the first state machine from an UPDATE-DR state is solely dependent upon a first TMS signal;

transferring first test data from the first module;

assigning the second module to be tested,

wherein the second module has a second state machine,

wherein the second state machine is compatible with the IEEE 1149.1 standard, and

wherein a transition of the second state machine from the UPDATE-DR state is solely dependent upon a second TMS signal;

transferring second test data from the second module;

using switching circuitry to control selection of the first and second modules;

tracking state history of the first state machine using a first duplicate state machine; and

tracking state history of the second state machine using a second duplicate state machine,

wherein the switching circuitry uses the state history of the first and second state machines to determine when the first module is to be coupled to a plurality of integrated circuit terminals and to determine when the second module is to be coupled to the plurality of integrated circuit terminals.

2. A method as in claim 1 , further comprising:

transferring the first TMS signal to the first module and not to the second module;

transitioning the first state machine from the UPDATE-DR state, wherein the transitioning of the first state machine from the UPDATE-DR state is dependent upon the first TMS signal and is independent of the second TMS signal;

duplicating, in the first duplicate state machine, the transitioning of the first state machine from the UPDATE-DR state;

generating the first test data in the first module;

transferring the second TMS signal to the second module and not to the first module;

transitioning the second state machine from the UPDATE-DR state, wherein the transitioning of the second state machine from the UPDATE-DR state is dependent upon the second TMS signal and is independent of the first TMS signal;

duplicating, in the second duplicate state machine, the transitioning of the second state machine from the UPDATE-DR state; and

generating the second test data in the second module.

3. A method as in claim 1 , wherein the first module, the second module, the first duplicate state machine, and the second duplicate state machine are all formed on the same integrated circuit.

4. A method as in claim 1 , wherein the switching circuitry performs switching in the UPDATE-DR state.

5. A method as in claim 1 , wherein the switching circuitry generates both the first TMS signal and the second TMS signal, and wherein the switching circuitry controls scan chain ordering of the first and second modules.

6. A method as in claim 1 , further comprising:

transferring the first TMS signal to the first module and not to the second module; and

transferring the second TMS signal to the second module and not to the first module,

wherein the first TMS signal and the second TMS signal are different signals.

7. A method as in claim 1 , further comprising:

transferring a first TDI signal to the first module and not to the second module; and

transferring a second TDI signal to the second module and not to the first module,

wherein the first TDI signal and the second TDI signal are not a same signal.

8. A method as in claim 1 , the method further comprising:

duplicating the transition of the first state machine from the UPDATE-DR state in the first duplicate state machine; and

duplicating the transition of the second state machine from the UPDATE-DR state in the second duplicate state machine.

9. A method as in claim 1 , further comprising:

transferring control information from a switch update register to the switching circuitry.

10. A method for testing a first module and a second module on a same integrated circuit, the method comprising:

assigning the first module to be tested,

wherein the first module has a first state machine,

wherein the first state machine is compatible with an IEEE 1149.1 standard, and

wherein a transition of the first state machine from an UPDATE-DR state is solely dependent upon a first TMS signal;

transferring first test data from the first module;

assigning the second module to be tested,

wherein the second module has a second state machine,

wherein the second state machine is compatible with the IEEE 1149.1 standard, and

wherein a transition of the second state machine from the UPDATE-DR state is solely dependent upon a second TMS signal;

transferring second test data from the second module;

using switching circuitry to control selection of the first and second modules;

tracking state history of the first state machine using a first duplicate state machine;

using the first duplicate state machine to generate a generated signature;

comparing the generated signature to a predetermined signature; and

in response to comparing the generated signature to the predetermined signature, determining selection of the first and second modules.

11. A method for testing a first module and a second module on a same integrated circuit, the method comprising:

selecting the first module to be tested,

wherein the first module has a first state machine,

wherein the first state machine is compatible with an IEEE 1149.1 standard, and

wherein a transition of the first state machine from an UPDATE-DR state is solely dependent upon a first TMS signal;

transferring first test data from the first module;

selecting the second module to be tested,

wherein the second module has a second state machine,

wherein the second state machine is compatible with the IEEE 1149.1 standard, and

wherein a transition of the second state machine from the UPDATE-DR state is solely dependent upon a second TMS signal;

transferring second test data from the second module;

tracking state history of the first state machine using a first duplicate state machine;

using the first duplicate state machine to generate a generated signature;

comparing the generated signature to a predetermined signature; and

in response to comparing the generated signature to the predetermined signature, determining selection of the first and second modules.

12. A method as in claim 11 , further comprising:

transferring the first TMS signal to the first module and not to the second module;

transitioning the first state machine from the UPDATE-DR state, wherein the transitioning of the first state machine from the UPDATE-DR state is dependent upon the first TMS signal and is independent of the second TMS signal;

duplicating, in the first duplicate state machine, the transitioning of the first state machine from the UPDATE-DR state;

generating the first test data in the first module;

transferring the second TMS signal to the second module and not to the first module;

transitioning the second state machine from the UPDATE-DR state, wherein the transitioning of the second state machine from the UPDATE-DR state is dependent upon the second TMS signal and is independent of the first TMS signal;

duplicating, in a second duplicate state machine, the transitioning of the second state machine from the UPDATE-DR state; and

generating the second test data in the second module.

13. A method as in claim 11 , wherein selection of the first module to be tested is performed in response to receiving a first extension via a first integrated circuit terminal, and wherein selection of the second module to be tested is performed in response to receiving a second extension via a second integrated circuit terminal, wherein the first extension is a same extension portion as the second extension, and wherein the first integrated circuit terminal is a same integrated circuit terminal as the second integrated circuit terminal.

14. A method as in claim 11 , wherein switching circuitry generates both the first TMS signal and the second TMS signal, and wherein the switching circuitry controls scan chain ordering of the first and second modules.

15. A method as in claim 14 , wherein the switching circuitry provides the first TMS signal to the first module and not to the second module, wherein the switching circuitry provides the second TMS signal to the second module and not to the first module, wherein the switching circuitry provides a first TDI signal to the first module and not to the second module, and wherein the switching circuitry provides a second TDI signal to the second module and not to the first module.

16. A method as in claim 11 , further comprising:

duplicating all transitions of the first state machine in the first duplicate state machine; and

duplicating all transitions of the second state machine in a second duplicate state machine.

17. A method as in claim 11 , wherein the step of using the first duplicate state machine to generate the generated signature comprises capturing a duplicated transition of the first duplicate state machine.

18. A method as in claim 11 , the method further comprising:

duplicating the transition of the first state machine from the UPDATE-DR state in the first duplicate state machine; and

duplicating the transition of the second state machine from the UPDATE-DR state in a second duplicate state machine.

19. A method as in claim 11 , further comprising:

using a value captured from an integrated circuit terminal along with state history of the first state machine to generate the generated signature.

20. A method for testing a first module and a second module on a same integrated circuit, the method comprising:

selecting the first module to be tested,

wherein the first module has a first state machine,

wherein the first state machine is compatible with an IEEE 1149.1 standard, and

wherein a transition of the first state machine from an UPDATE-DR state is solely dependent upon a first TMS signal;

transferring first test data from the first module;

selecting the second module to be tested,

wherein the second module has a second state machine,

wherein the second state machine is compatible with the IEEE 1149.1 standard, and

wherein a transition of the second state machine from the UPDATE-DR state is solely dependent upon a second TMS signal;

transferring second test data from the second module;

tracking state history of the first state machine using a first duplicate state machine; and

tracking state history of the second state machine using a second duplicate state machine,

wherein switching circuitry uses the state history of the first and second state machines to determine when the first module is to be coupled to a plurality of integrated circuit terminals and to determine when the second module is to be coupled to the plurality of integrated circuit terminals.