IP Library › Granted Patent US 7,606,078
Granted Patent B2
US 7,606,078 · App. 11/636,382 · Granted Oct 20, 2009

Method for programming of memory cells, in particular of the flash type, and corresponding programming architecture

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Quick Facts
Patent No.
US 7,606,078
App. No.
11/636,382
Filed
Dec 8, 2006
Granted
Oct 20, 2009
Kind
B2
Examiner
TRAN, ANTHAN
Art Unit
2827
USPC
365/185.22
Abstract

A method is described for programming memory cells, in particular of the Flash type. In accordance with the method, a verification is performed with a first parallelism (M) in which a reading is carried out for determining the state of a group of memory cells, a determination is performed of a programming parallelism (np), based on the results of the verification, and a real programming of the memory cells carried out with the programming parallelism (np). An architecture is also described for programming memory cells in particular of the Flash type.

Claims (22)

1. A flash memory comprising:

a plurality of cells;

at least one microcontroller to selectively program a first number of said cells at a time or a second number of cells at a time, said first and second numbers being different;

a counter and a verify block coupled to said counter;

a combinatorial portion to generate a control flag to select the first or second number of cells;

a charge pump; and

a register having a second parallelism corresponding to a driving capability value of the charge pump according to the relation:

n=Icharge_pump/Icell

wherein

Icharge_pump is a maximum value of the current which can be supplied by the charge pump, and

Icell is a value of the current absorbed by a memory cell during a programming.

2. The memory of claim 1 , wherein the counter to supply the combinatorial portion with a number corresponding to a number of memory cells needing to be programmed as verified by the verify block.

3. The memory of claim 1 , wherein the combinatorial portion receives at the input and compares the number of cells to be programmed and the second parallelism stored in the register and generates the control flag according to the following relations:

PR_PAGE=1 if the number of memory cells to be programmed is lower or equal to the second parallelism (bit_to_pr<=n); and

PR_PAGE=0 if the number of memory cells to be programmed is higher than the second parallelism (bit_to_pr>n).

4. The memory of claim 1 , wherein the microcontroller carries out the programming operation according to a programming parallelism determined on the basis of the control flag according to the following rules:

if PR_PAGE=1, attribution to the programming parallelism of a value corresponding to a value of maximum parallelism (np=M); and

if PR_PAGE=0 attribution to the programming parallelism of a value corresponding to a value of minimum parallelism (np=n).

5. The memory of claim 4 , wherein the value of maximum parallelism corresponds to the first parallelism.

6. The memory of claim 4 , wherein the value of minimum parallelism corresponds to the second parallelism.

7. The memory of claim 1 , wherein the microcontroller carries out the programming operation according to a programming parallelism determined in a dichotomic way according to the relation:

if the number of memory cells to be programmed is higher than the second parallelism (bit_to_pr=n), attribution to the programming parallelism of a value corresponding to half of the value of maximum parallelism (np=M/2), this relation being consecutively applied up to exhaustion of the cells to be programmed.