Reverse set with current limit for non-volatile storage
View Patent ↗A storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The memory cell is SET in a reverse biased fashion.
1. A storage system, comprising:
a reversible resistance-switching memory cell;
a current limiting circuit;
a first control line in communication with the reversible resistance-switching memory cell;
a first selection circuit in communication with the first control line, the first selection circuit selectively provides a first signal to the reversible resistance-switching memory cell;
a second control line in communication with the reversible resistance-switching memory cell; and
a second selection circuit in communication with the second control line, the second selection circuit selectively connects the second control line to the current limiting circuit while the first selection circuit provides the first signal to reversible resistance-switching memory cell to provide a reverse bias to the reversible resistance-switching memory cell that will set the reversible resistance-switching memory cell to a low resistance state.
2. The storage system of claim 1 , wherein:
the current limiting circuit includes a first node, a current mirror having an output at the first node and a comparator in communication with the first node; and
the first node is in communication with the second control line via the second selection circuit.
3. The storage system of claim 2 , wherein:
current into the first node from the second control line is indicative of current through the reversible resistance-switching memory cell;
the current mirror operates to mirror a reference current;
as current into the first node from the second control line approaches the reference current a voltage at the first node moves toward a reference voltage; and
the comparator compares the voltage at the first node with the reference voltage.
4. The storage system of claim 3 , wherein:
the current limiting circuit includes a switch in communication with and controlled by an output of the comparator to selectively assert a signal on the second control line to deselect the reversible resistance-switching memory cell from being subjected to a condition for setting the reversible resistance-switching memory cell to the low resistance state.
5. The storage system of claim 4 , wherein:
the reversible resistance-switching memory cell is associated with a current limit for an operation that sets the reversible resistance-switching memory cell to the low resistance state; and
the reference current is indicative of the current limit.
6. The storage system of claim 4 , wherein:
the reversible resistance-switching memory cell includes a diode and reversible resistance-switching material.
7. The storage system of claim 4 , wherein:
the reversible resistance-switching memory cell is non-volatile.
8. The storage system of claim 4 , further comprising:
an additional plurality of memory cells, the reversible resistance-switching memory cell and the additional plurality of memory cells comprise a monolithic three dimensional memory array.
9. The storage system of claim 1 , further comprising:
a read circuit in communication with the reversible resistance-switching memory cell.
10. The storage system of claim 1 , wherein:
the reversible resistance-switching memory cell includes a steering device and reversible resistance-switching material.
11. The storage system of claim 10 , wherein:
the reversible resistance-switching material comprises metal oxide; and
the steering device is a diode.
12. A storage system, comprising:
a non-volatile memory cell;
a first control line in communication with the memory cell;
a first selection circuit in communication with the first control line, the first selection circuit selectively provides a first signal to the memory cell;
a second control line in communication with the memory cell;
a second selection circuit in communication with the second control line, the second selection circuit selectively provides a second signal to the memory cell while the first selection circuit provides the first signal to the memory cell to provide a reverse bias to the memory cell that will set the memory cell to a low resistance state; and
a current limiting circuit in communication with the memory cell.
13. The storage system of claim 12 , wherein:
the current limiting circuit includes a first node, a current mirror having an output at the first node and a comparator in communication with the first node; and
the first node is in communication with the second control line via the second selection circuit.
14. The storage system of claim 13 , wherein:
current into the first node from the second control line is indicative of current through the memory cell;
the current mirror operates to mirror a reference current;
as current into the first node from the second control line approaches the reference current a voltage at the first node moves toward a reference voltage; and
the comparator compares the voltage at the first node with the reference voltage.
15. The storage system of claim 12 , wherein:
the current limiting circuit includes a switch to selectively assert a signal on the second control line to deselect the memory cell from being subjected to a condition for setting the memory cell to the low resistance state.
16. The storage system of claim 12 , wherein:
the reversible resistance-switching memory cell includes a diode and metal oxide material.
17. A method for operating a storage system, comprising:
setting a reversible resistance-switching nonvolatile storage memory cell to a low resistance state by reverse biasing the reversible resistance-switching nonvolatile storage memory cell; and
limiting current through the reversible resistance-switching nonvolatile storage memory cell using a current limiting circuit while setting the reversible resistance-switching nonvolatile storage memory cell to the low resistance state.
18. The method of claim 17 , wherein setting the reversible resistance-switching nonvolatile storage memory cell to the low resistance state comprises:
biasing word lines and bit lines for a monolithic three dimensional memory array to a first voltage level, the monolithic three dimensional memory array includes the reversible resistance-switching nonvolatile storage memory cell as well as other reversible resistance-switching storage memory cell;
biasing a selected word line to at least a diode drop higher than the first voltage level; and
connecting a selected bit line to the current limiting circuit with a path to ground.
19. The method of claim 18 , wherein limiting current through the reversible resistance-switching nonvolatile storage memory cell comprises:
operating a current mirror connected to the selected bit line via a first node;
monitoring the voltage at the first node;
comparing the voltage at the first node to a reference voltage; and
applying a save voltage to the selected bit line when the voltage at the first node is at a predetermined level with respect to the reference voltage.
20. The method of claim 19 , wherein limiting current through the reversible resistance-switching nonvolatile storage memory cell further comprises:
disabling a reference current input for the current mirror when the voltage at the first node is at a predetermined level with respect to the reference voltage.
21. The method of claim 19 , wherein:
the current mirror includes a reference current input that is mirrored at an output of the current mirror, the reference current input is equal to a current limit for setting the reversible resistance-switching nonvolatile storage memory cell to the low resistance state.
22. A method for operating a storage system, comprising:
setting a reversible resistance-switching nonvolatile storage memory cell to a low resistance state including providing a first signal to a first terminal of the reversible resistance-switching nonvolatile storage memory cell and providing a second signal to a second terminal of the reversible resistance-switching nonvolatile storage memory cell to cause a current through the reversible resistance-switching nonvolatile storage memory cell in a direction that is reverse of easiest current flow through the reversible resistance-switching nonvolatile storage memory cell; and
limiting current through the reversible resistance-switching nonvolatile storage memory cell using a current limiting circuit while setting the reversible resistance-switching nonvolatile storage memory cell to the low resistance state.
23. The method of claim 22 , wherein setting the reversible resistance-switching nonvolatile storage memory cell to the low resistance state comprises:
biasing word lines and bit lines for a monolithic three dimensional memory array to a first voltage level, the monolithic three dimensional memory array includes the reversible resistance-switching nonvolatile storage memory cell as well as other reversible resistance-switching storage memory cell;
biasing a selected word line to at least a diode drop higher than the first voltage level; and
connecting a selected bit line to the current limiting circuit with a path to ground.
24. The method of claim 22 , wherein limiting current through the reversible resistance-switching nonvolatile storage memory cell comprises:
operating a current mirror in communication with the reversible resistance-switching nonvolatile storage memory cell via a first node;
monitoring the voltage at the first node;
comparing the voltage at the first node to a reference voltage; and
asserting a signal on the second control line to deselect the reversible resistance-switching nonvolatile storage memory cell from being subjected to a condition for setting to the low resistance state.
25. The method of claim 24 , wherein limiting current through the reversible resistance-switching nonvolatile storage memory cell further comprises:
disabling the reference current input for the current mirror when the voltage at the first node is at a predetermined level with respect to the reference voltage.
26. The method of claim 22 , wherein setting the reversible resistance-switching nonvolatile storage memory cell to the low resistance state comprises:
biasing unselected word lines and unselected bit lines to ground;
biasing a selected word line to one side of ground; and
providing a selected bit line with a path to a voltage at the other side of ground.