Single event transient mitigation and measurement in integrated circuits
View Patent ↗A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements.
1. A computer program product in a computer-readable medium for use in a data processing system for programming a programmable logic integrated circuit device, the device having programmable elements, including programmable elements corresponding to logical sequential elements, and control elements associated with the programmable elements, the computer program product comprising:
first instructions for converting the user design into programmable elements, wherein at least some of the sequential elements are converted into programmable elements forming an SEU mitigated sequential element with an SET filter on at least one input; and
second instructions for generating the data structure required for programming the control elements in the programmable logic device.
2. The computer program product of claim 1 , further comprising third instructions for identifying the sequential elements in an end user design requiring SET filtering and SEU mitigation, whereby the first instructions convert only the identified programmable elements forming an SEU mitigated sequential element with an SET filter on at least one input.
3. The computer program product of claim 2 , wherein the third instructions identify all the sequential elements in an end user design as requiring SET filtering and SEU mitigation.
4. The computer program product of claim 1 , wherein all of the sequential elements are converted into programmable elements forming an SEU mitigated sequential element with an SET filter on at least one input.
5. The computer program product of claim 4 , further comprising third instructions for applying the data structure to the integrated circuit device.
6. The computer program product of claim 3 , further comprising fourth instructions for applying the data structure to the integrated circuit device.
7. The computer program product of claim 2 , further comprising fourth instructions for applying the data structure to the integrated circuit device.
8. The computer program product of claim 1 , further comprising third instructions for applying the data structure to the integrated circuit device.