Integrated circuit with phase-change memory cells and method for addressing phase-change memory cells
View Patent ↗The present invention relates to an integrated circuit comprising a plurality of bitlines (b 1 ) and a plurality of word-lines (w 1 ) as well as a plurality of memory-cells (MC) coupled between a separate bit-line/word-line pair of the plurality of bit-lines (b 1 ) and wordlines (w 1 ) for storing data in the memory cell. Each memory cell (MC) comprises a selecting unit (T) and a programmable resistance (R). The value of the phase-change resistance (R) is greater than the value of a first phase-change resistance (R opt ) defined by a supply voltage (V dd ) divided by a maximum drive current (I m ) through said first phase-change resistor (R opt ).
1. Integrated circuit, comprising:
a plurality of bit-lines (bl), a plurality of word-lines (wl), and a plurality of memory cells (MC) coupled between a separate bit-line/word-line pair of the plurality of bit-lines (bl) and word-lines (wl) for storing data in a selected memory cell (MC);
wherein each memory cell (MC) comprises:
a selecting unit (T) with an effective resistance of V dd /I m , where V dd is a supply voltage of the selected memory cell (MC) applied to each of the bit-lines (bl) and the word-lines (wl), and I m is a maximum drive current (I m ) of the selecting unit (T); and
a programmable phase-change resistor (R) with a resistance of R pc ;
wherein a ratio of the resistance R pc of the phase-change resistor (R) relative to the effective resistance V dd /I m of the selecting unit (T) is greater than 1, as follows:
R pc *I m /V dd >1,
where ‘*’ represents a multiplication operation and ‘/’ represents a division operation.
2. Integrated circuit according to claim 1 , wherein said ratio corresponds to about 1.2 to about 2.2.
3. Integrated circuit according to claim 1 , wherein the ratio is 1.8.
4. Integrated circuit according to claim 1 , wherein a bit-line voltage and a word-line voltage are lowered for a SET operation on the selected memory cell (MC).
5. Method of addressing a selected memory cell (MC) within an array of memory cells (MC) with bit-lines (bl) and word-lines (wl), wherein each memory cell (MC) comprises:
a selecting unit (T) with an effective resistance of V dd /I m , where V dd is a supply voltage of the selected memory cell (MC) applied to each of the bit-lines (bl) and the word-lines (wl), and I m is a maximum drive current (I m ) of the selecting unit (T); and
a programmable phase-change resistance (R) with a resistance of R pc ;
wherein a ratio of the resistance R pc of the phase-change resistor (R) relative to the effective resistance V dd /I m of the selecting unit (T) is greater than 1, as follows:
R pc *I m /V dd >1,
where ‘*’ represents a multiplication operation and ‘/’ represents a division operation.
6. Method according to claim 5 , wherein a bit-line voltage and a word-line voltage are lowered for a SET operation on the selected memory cell (MC).
7. Integrated circuit according to claim 1 , wherein said ratio corresponds to about 1.5 to about 2.2.