Method of erasing a resistive memory device
View Patent ↗In a first method of erasing a resistive memory device, an electrical potential is applied to the gate of a transistor in series with the resistive memory device, and successive increasing currents are provided through the resistive memory device by means of providing successive increasing electrical potentials across the resistive memory device. In a second method of erasing a resistive memory device, an electrical potential is applied across the resistive memory device, and successive increasing currents are provided through the resistive memory device by means of providing successive increasing electrical potentials to the gate of a transistor in series with the resistive memory device.
1. A method of erasing a resistive memory device which may have a plurality of successive increasing pulsed electrical potentials applied across the resistive memory device, comprising:
applying the minimum number of successive electrical potentials across the resistive memory device to erase the resistive memory device; and
sensing a state of the resistive memory device after each application of electrical potential, wherein a current control device connected to the resistive memory device controls current through the resistive memory device.
2. The method of claim 1 wherein erasing of the resistive memory device comprises moving electronic charge carriers in the resistive memory device.
3. The method of claim 1 wherein sensing the state of the resistive memory device comprises reading the state of the resistive memory device.
4. The method of claim 1 and further comprising a plurality of said memory devices making up an array thereof.
5. The method of claim 4 and further comprising select devices in the array.
6. The method of claim 5 wherein the select devices are diodes.
7. The method of claim 5 wherein the select devices are transistors.
8. The method of claim 1 and further comprising said memory device incorporated in a system.
9. The method of claim 8 wherein the system is selected from the group consisting of a hand-held device, a vehicle, and a computer.
10. A method of erasing a resistive memory device comprising:
applying an electrical potential across the resistive memory device; and
applying increasing electrical potential to the gate of a transistor operatively associated with the resistive memory device to erase the resistive memory device, wherein a state of the resistive memory device is sensed after each application of increasing electrical potential, and wherein a current control device connected to the resistive memory device controls current through the resistive memory device.
11. The method of claim 10 wherein the increasing electrical potential is a series of pulsed electrical potentials.
12. The method of claim 10 and further comprising said memory device incorporated in a system.
13. The method of claim 12 wherein the system is selected from the group consisting of a hand-held device, a vehicle, and a computer.
14. A method of erasing a resistive memory device comprising:
applying an electrical potential across the resistive memory device; and
applying successive electrical potentials to the gate of a transistor operatively associated with the resistive memory device to erase the resistive memory device, wherein a state of the resistive memory device is sensed after each application of electrical potential, and wherein a current control device connected to the resistive memory device controls current through the resistive memory device.
15. The method of claim 14 wherein the successive electrical potentials are successive increasing electrical potentials.
16. The method of claim 15 wherein the successive increasing potentials are pulsed electrical potentials.
17. The method of claim 14 wherein erasing of the resistive memory device comprises moving electronic charge carriers in the resistive memory device.
18. The method of claim 14 wherein the resistive memory device and transistor are in series.
19. The method of claim 14 wherein sensing the state of the resistive memory device comprises reading the state of the resistive memory device.
20. The method of claim 14 and further comprising a plurality of said memory devices making up an array thereof.
21. The method of claim 20 and further comprising select devices in the array.
22. The method of claim 21 wherein a plurality of transistors operatively associated with said memory devices act as the select devices.
23. A method of erasing a resistive memory device comprising:
applying a series of successive increasing pulsed currents through the resistive memory device; and
sensing the state of the resistive memory device after each application of current, wherein a current control device connected to the resistive memory device controls current through the resistive memory device.