Semiconductor package system with substrate having different bondable heights at lead finger tips

1. A semiconductor package system comprising:

providing a die attach paddle;

providing a first plurality of leads around the die attach paddle having a first plurality of lead tips;

providing a second plurality of leads around the die attach paddle interleaved with the first plurality of leads, at least some of the second plurality of leads having a plurality of depression lead tips;

attaching a first die to the die attach paddle;

wire bonding the die to the first plurality of leads and the second plurality of leads, having wires bonding to the tops of the depression lead tips; and

encapsulating the die.

2. The semiconductor package system as claimed in claim 1 , further comprising:

attaching a second die to the first die; and

wire bonding the second die to the first plurality of leads and the second plurality of leads.

3. The semiconductor package system as claimed in claim 1 , wherein:

providing the plurality of depression lead tips provides a plurality of depression lead tips about half the thickness of the first plurality of lead tips.

4. The semiconductor package system as claimed in claim 1 , wherein:

providing the plurality of depression lead tips uses at least one of a coining process, an etching process, and combinations thereof.

5. A semiconductor package system, comprising:

providing a die attach paddle;

providing a plurality of outer leads around the periphery of the die attach paddle;

providing a plurality of inner leads around the periphery of the die attach paddle;

providing a plurality of depression lead tips on at least some of the inner leads;

attaching a first die to the die attach paddle;

wire bonding the first die to the plurality of outer leads and the plurality of depression lead tips, having wires bonding to the tops of the depression lead tips; and

encapsulating the die, the plurality of outer leads, and the plurality of inner leads.

6. The semiconductor package system as claimed in claim 5 , further comprising:

attaching a second die to the first die; and

wire bonding the second die to the plurality of outer leads and the plurality of depression lead tips.

7. The semiconductor package system as claimed in claim 5 , wherein:

providing the plurality of depression lead tips provides a plurality of depression lead tips about half the thickness of the outer leads.

8. The semiconductor package system as claimed in claim 5 , wherein:

providing the plurality of depression lead tips uses at least one of a coining process, an etching process, and combinations thereof.

9. The semiconductor package system as claimed in claim 5 , further comprising:

interleaving the plurality of outer leads with the plurality of inner leads.

10. A semiconductor package system comprising:

a die attach paddle;

a first plurality of leads having a first plurality of lead tips around the die attach paddle;

a second plurality of leads interleaved with the first plurality of leads, at least some of the second plurality of leads having a plurality of depression lead tips;

a first die attached to the die attach paddle;

a first plurality of wires bonding the die to the first plurality of leads and the second plurality of leads, having a portion of the first plurality of wires bonding to the tops of the depression lead tips; and

an encapsulant encapsulating the die.

11. The semiconductor package system as claimed in claim 10 , further comprising:

a second die attached to the first die; and

a second plurality of wires bonding the second die to the first plurality of leads and the second plurality of leads.

12. The semiconductor package system as claimed in claim 10 , wherein:

the plurality of depression lead tips comprises a plurality of depression lead tips about half the thickness of the first plurality of lead tips.

13. The semiconductor package system as claimed in claim 10 , wherein:

the plurality of depression lead tips is characterized by having been flattened by coining, etching, or a combination thereof.

14. The semiconductor package system as claimed in claim 10 , wherein:

the first plurality of leads comprises a plurality of outer leads;

the second plurality of leads comprises a plurality of inner leads; and

an encapsulant encapsulating the die, the plurality of outer leads, and the plurality of inner leads.

15. The semiconductor package system as claimed in claim 14 , further comprising:

a second die attached to the first die; and

wires bonding the second die to the plurality of outer leads and the plurality of depression lead tips.

16. The semiconductor package system as claimed in claim 14 , wherein:

the plurality of depression lead tips comprises a plurality of depression lead tips about half the thickness of the outer leads.

17. The semiconductor package system as claimed in claim 14 , wherein:

the plurality of depression lead tips is characterized by having been flattened by coining, etching, or a combination thereof.

18. The semiconductor package system as claimed in claim 14 , wherein:

the plurality of outer leads is interleaved with the plurality of inner leads.