Integrated circuit package on package system

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Quick Facts

Patent No.: US 7,986,043
App. No.: 11/276,646
Filed: Mar 8, 2006
Granted: Jul 26, 2011
Kind: B2
Examiner: ARORA, AJAY
Art Unit: 2892
USPC: 257/777

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Abstract

An integrated circuit package on package system including forming an interconnect integrated circuit package and attaching an extended-lead integrated circuit package on the interconnect integrated circuit package wherein a mold cap of the extended-lead integrated circuit package faces a mold cap of the interconnect integrated circuit package.

Claims (33)

1. A method of manufacture of an integrated circuit package on package system comprising:

forming an interconnect integrated circuit package having an integrated circuit and an interconnect package encapsulant on a substrate;

forming an extended-lead integrated circuit package having an extended-lead package encapsulant with a die paddle exposed and an extended lead having an extension from the extended-lead package encapsulant with clearance for the interconnect package encapsulant;

attaching the extended-lead to the substrate with the extended-lead package encapsulant facing the interconnect package encapsulant; and

applying a package encapsulant over and on the substrate locking the extended lead to the substrate, locking the interconnect package encapsulant to the substrate, and locking the extended lead to the extended-lead package encapsulant with the extended lead exposed from both the package encapsulant and the extended-lead package encapsulant.

2. The method as claimed in claim 1 further comprising attaching a top integrated circuit package on the extended-lead integrated circuit package.

3. The method as claimed in claim 1 wherein attaching the extended-lead integrated circuit package comprises forming an extended-lead leadframe having extended leads formed towards a top surface of a die paddle.

4. The method as claimed in claim 1 wherein attaching the extended-lead integrated circuit package comprises forming an extended-lead leadframe of the extended-lead integrated circuit package as an interposer.

5. The method as claimed in claim 1 further comprising attaching a quad flat no lead package on the extended lead integrated circuit package.

6. A method of manufacture of an integrated circuit package on package system comprising:

forming an interconnect integrated circuit package having an integrated circuit and an interconnect package encapsulant on a mounting surface of a substrate;

attaching the extended lead to the mounting surface of the substrate with the extended-lead integrated circuit package over the interconnect integrated circuit package; and

applying a package encapsulant over and on the substrate locking the extended lead to the substrate, locking the interconnect package encapsulant to the substrate, and locking the extended-lead to the extended-lead package encapsulant with the extended lead exposed from both the package encapsulant and the extended-lead package encapsulant.

7. The method as claimed in claim 6 wherein attaching the extended-lead integrated circuit package comprises forming a connectivity surface of an extended-lead leadframe of the extended-lead integrated circuit package.

8. The method as claimed in claim 6 further comprising attaching a top integrated circuit package on a connectivity surface of the extended-lead leadframe.

9. The method as claimed in claim 6 wherein attaching the extended-lead integrated circuit package comprises a surface mount process.

10. The method as claimed in claim 6 wherein attaching the extended-lead integrated circuit package comprises applying an encapsulant with a connectivity surface of an extended-lead leadframe substantially exposed.

11. An integrated circuit package on package system comprising:

an interconnect integrated circuit package having an integrated circuit and an interconnect package encapsulant on a substrate;

an extended-lead integrated circuit package having an extended-lead package encapsulant with a die paddle exposed and an extended lead having an extension from the extended-lead package encapsulant with clearance for the integrated circuit, the extended lead attached to the substrate with the extended-lead package encapsulant facing the interconnect package encapsulant; and

a package encapsulant over and on the substrate locking the extended lead to the substrate, locking the interconnect package encapsulant to the substrate, and locking the extended lead to the extended-lead package encapsulant with the extended lead exposed from both the package encapsulant and the extended-lead package encapsulant.

12. The system as claimed in claim 11 further comprising a top integrated circuit package on the extended-lead integrated circuit package.

13. The system as claimed in claim 11 wherein the extended-lead integrated circuit package comprises an extended-lead leadframe having extended leads formed towards a top surface of a die paddle.

14. The system as claimed in claim 11 wherein the extended-lead integrated circuit package comprises an extended-lead leadframe of the extended-lead integrated circuit package as an interposer.

15. The system as claimed in claim 11 further comprising a quad flat no lead package attached on the extended-lead integrated circuit package.

16. The system as claimed in claim 11 wherein:

the interconnect integrated circuit package is an interconnect integrated circuit package having the integrated circuit on the substrate; and

the extended-lead integrated circuit package is an extended-lead integrated circuit package over the interconnect integrated circuit package having the extended lead on the substrate.

17. The system as claimed in claim 16 wherein the extended-lead integrated circuit package comprises a connectivity surface of an extended-lead leadframe of the extended-lead integrated circuit package.

18. The system as claimed in claim 16 further comprising a top integrated circuit package on a connectivity surface of the extended-lead leadframe.

19. The system as claimed in claim 16 wherein the extended-lead integrated circuit package is a surface mounted extended-lead package.

20. The system as claimed in claim 16 wherein the extended-lead integrated circuit package comprises an encapsulant with a connectivity surface of an extended-lead leadframe substantially exposed.