IP Library › Granted Patent US 8,012,867
Granted Patent B2
US 8,012,867 · App. 11/618,647 · Granted Sep 6, 2011

Wafer level chip scale package system

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Quick Facts
Patent No.
US 8,012,867
App. No.
11/618,647
Filed
Dec 29, 2006
Granted
Sep 6, 2011
Kind
B2
Art Unit
2895
USPC
438/465
Abstract

A wafer level chip scale package system is provided including placing a first integrated circuit over a semiconductor wafer having a second integrated circuit; connecting a second electrical interconnect between the first integrated circuit and the second integrated circuit; forming a stress relieving encapsulant on the outer perimeter of the second integrated circuit for covering the second electrical interconnect; and singulating a chip scale package, from the semiconductor wafer, through the stress relieving encapsulant and the semiconductor wafer.

Claims (58)

1. A method for manufacturing a wafer level chip scale package system comprising:

forming a base package including:

forming a package substrate,

coupling a first integrated circuit to the package substrate, and

forming a molded cap on the first integrated circuit and the package substrate;

adhesively bonding the molded cap directly to a semiconductor wafer having a second integrated circuit;

connecting a second electrical interconnect between the first integrated circuit and the second integrated circuit including directly coupling an active surface of the second integrated circuit and a system side of the package substrate by the second electrical interconnect;

forming a stress relieving encapsulant on the outer perimeter of the second integrated circuit for covering the second electrical interconnect; and

singulating a chip scale package, from the semiconductor wafer, through the stress relieving encapsulant and the semiconductor wafer.

2. The method as claimed in claim 1 further comprising forming a second wire bond pad and a contact pad on a system side of the package substrate.

3. The method as claimed in claim 1 further comprising applying a dam material around the semiconductor wafer and over the edge of a base package for forming a reservoir.

4. The method as as claimed in claim 1 further comprising forming a system interconnect on a base package includes connecting electrically the base package, the first integrated circuit, the second integrated circuit, or a combination thereof.

5. The method as claimed in claim 1 further comprising forming a package on package structure comprising:

forming a stacking substrate having a third integrated circuit electrically coupled thereto;

forming a first system interconnect between a component side of the stacking substrate and the chip scale package; and

providing a second system interconnect on the system side of the stacking substrate for connecting electrically a printed circuit board, the first integrated circuit, the second integrated circuit, the third integrated circuit, or a combination thereof.

6. A method for manufacturing a wafer level chip scale package system comprising:

forming a base package having an first integrated circuit electrically connected to a package substrate including encapsulating the first integrated circuit, a first electrical interconnect, and a component side of the package substrate by a molded cap;

adhesively bonding the molded cap directly to a semiconductor wafer having a second integrated circuit including applying a pick and place machine for positioning the base package on an active surface of the second integrated circuit;

connecting a second electrical interconnect electrically between the base package and the second integrated circuit including bonding a bond wire between the active surface of the second integrated circuit and a system side of the package substrate;

forming a stress relieving encapsulant on the outer perimeter of the second integrated circuit for covering the second electrical interconnect includes molding an under-fill material; and

singulating a chip scale package from the semiconductor wafer by sawing through the stress relieving encapsulant and the semiconductor wafer.

7. The method as claimed in claim 6 wherein forming the base package includes forming the package substrate having a second wire bond pad and a contact pad on the system side of the package substrate.

8. The method as claimed in claim 6 further comprising applying a dam material around the semiconductor wafer and over the edge of a base package for forming a reservoir including filling the reservoir with the stress relieving encapsulant.

9. The method as claimed in claim 6 further comprising forming a system interconnect on the base package includes connecting electrically the base package, the first integrated circuit, the second integrated circuit, or a combination thereof by attaching a bond wire between the second integrated circuit and the system side of the package substrate.

10. The method as claimed in claim 6 further comprising forming a package on package structure comprising:

forming a stacking substrate having a third integrated circuit electrically coupled thereto including providing a first contact pad on. the component side and a second contact pad on the system side of the stacking substrate;

forming a first system interconnect between the component side of the stacking substrate and the chip scale package including forming a solder ball, a solder column, or a stud bump; and

providing a second system interconnect on the system side of the stacking substrate for connecting electrically a printed circuit board, the first integrated circuit, the second integrated circuit, the third integrated circuit, or a combination thereof.

11. A wafer level chip scale package system comprising:

a base package including:

a package substrate,

a first integrated circuit coupled to the package substrate, and

a molded cap formed on the first integrated circuit and the package substrate;

a semiconductor wafer having a second integrated circuit and having the molded cap adhesively bonded directly thereto;

a second electrical interconnect connected between the first integrated circuit and the second integrated circuit;

a stress relieving encapsulant formed on the outer perimeter of the second integrated circuit for covering the second electrical interconnect; and

a chip scale package singulated, from the semiconductor wafer, through the stress relieving encapsulant and the semiconductor wafer; and

wherein:

the second electrical interconnect is a bond wire; and

the stress relieving elcapsulant is an under-fill material, including:

the bond wire between an active surface of the second integrated circuit and a system side of the package substrate, and

the under-fill material molded on the outer perimeter of the second integrated circuit over the bond wire.

12. The system as claimed in claim 11 further comprising a second wire bond pad and a contact pad on a system side of the package substrate.

13. The system as claimed in claim 11 further comprising a dam material around the semiconductor wafer and over the edge of a base package for forming a reservoir.

14. The system as claimed in claim 11 further comprising a system interconnect on a base package includes the base package, the first integrated circuit, the second integrated circuit, or a combination thereof connected electrically.

15. The system as claimed in claim 11 further comprising a package on package structure comprising:

a stacking substrate having a third integrated circuit electrically coupled thereto;

a first system interconnect between the component side of the stacking substrate and the chip scale package; and

a second system interconnect on the system side of the stacking substrate for connecting electrically a printed circuit board, the first integrated circuit, the second integrated circuit, the third integrated circuit, or a combination thereof.

16. The system as claimed in claim 11 wherein the molded cap on the first integrated circuit is formed on a first electrical interconnect and a component side of the package substrate.

17. The system as claimed in claim 16 wherein the base package includes the package substrate having a second wire bond pad and a contact pad on the system side of the package substrate.

18. The system as claimed in claim 16 further comprising a dam material around the semiconductor wafer and over the edge of a base package for forming a reservoir including the reservoir filled with the stress relieving encapsulant.

19. The system as claimed in claim 16 further comprising a system interconnect on the base package includes the base package, the first integrated circuit, the second integrated circuit, or a combination thereof connected electrically by a bond wire between the second integrated circuit and the system side of the package substrate.

20. The system as claimed in claim 16 further comprising a package on package structure comprising:

a stacking substrate having a third integrated circuit electrically coupled thereto, including a first contact pad on the component side and a second contact pad on the system side of the stacking substrate;

a first system interconnect between the component side of the stacking substrate and the chip scale package includes a solder ball, a solder column, or a stud bump; and

a second system interconnect on the system side of the stacking substrate for connecting electrically a printed circuit board, the first integrated circuit, the second integrated circuit, the third integrated circuit, or a combination thereof.