Embedded integrated circuit package system and method of manufacture thereof

1. A method of manufacture of an embedded integrated circuit package system comprising:

forming a first structure having a first conductive pattern with a support;

connecting a first integrated circuit die having bumps directly on the first conductive pattern, the first integrated circuit die supported by the support;

forming a substrate forming encapsulation to cover the first integrated circuit die and the first conductive pattern;

forming a channel in the substrate forming encapsulation; and

applying a conductive material in the channel.

2. The method as claimed in claim 1 further comprising:

attaching a second structure on the substrate forming encapsulation;

wherein:

forming the channel in the substrate forming encapsulation comprises:

forming the channel between the second structure and the first conductive pattern; and

applying the conductive material in the channel further comprises:

forming a second conductive pattern exposed through the second structure,

and

forming an electrical via between the first conductive pattern and the second conductive pattern.

3. The method as claimed in claim 1 further comprising:

attaching a second structure on the substrate forming encapsulation;

forming a terminal pad from a portion of the first conductive pattern exposed through the first structure;

mounting a component on the terminal pad; and

wherein:

forming the channel in the substrate forming encapsulation comprises:

forming the channel between the second structure and the first conductive pattern; and

applying the conductive material in the channel further comprises:

forming a second conductive pattern exposed through the second structure,

and

forming an electrical via between the first conductive pattern and the second conductive pattern.

4. The method as claimed in claim 1 further comprising:

connecting a component on the first conductive pattern;

stacking a second integrated circuit die on the first integrated circuit die;

attaching a second structure on the substrate forming encapsulation;

forming a terminal pad from a portion of the first conductive pattern exposed through the first structure; and

wherein:

forming the channel in the substrate forming encapsulation comprises:

forming the channel between the second structure and the first conductive pattern; and

applying the conductive material in the channel further comprises:

forming a second conductive pattern exposed through the second structure,

and

forming an electrical via between the first conductive pattern and the second conductive pattern.

5. A method of manufacture of an embedded integrated circuit package system comprising:

forming a first structure having a first conductive pattern with a support and a contact;

connecting a first integrated circuit die having bumps directly on the contact, the first integrated circuit die supported by the support;

molding a substrate forming encapsulation to cover the first integrated circuit die and the first conductive pattern;

forming a channel in the substrate forming encapsulation; and

plating a conductive material in the channel.

6. The method as claimed in claim 5 wherein forming the first conductive pattern comprises:

forming the support on the first integrated circuit die;

forming a contact having the first integrated circuit die thereon; and

forming a trace to connect the first integrated circuit die.

7. The method as claimed in claim 5 wherein applying the conductive material in the channel includes forming a vertical shield in the substrate forming encapsulation.

8. The method as claimed in claim 5 further comprising:

attaching a second structure on the substrate forming encapsulation;

wherein:

applying the conductive material in the channel further comprises:

forming a second conductive pattern exposed through the second structure;

and

connecting an external interconnect to the second conductive pattern.

9. An embedded integrated circuit package system comprising:

a first structure having a first conductive pattern with a support;

a first integrated circuit die having bumps coupled directly on the first conductive pattern, the first integrated circuit die supported by the support;

a substrate forming encapsulation to cover the first integrated circuit die and the first conductive pattern;

a channel in the substrate forming encapsulation; and

a conductive material in the channel.

10. The system as claimed in claim 9 further comprising:

a second structure on the substrate forming encapsulation;

wherein:

the channel in the substrate forming encapsulation comprises:

the channel between the second structure and the first conductive pattern; and

the conductive material in the channel further comprises:

a second conductive pattern exposed through the second structure, and

an electrical via between the first conductive pattern and the second conductive pattern.

11. The system as claimed in claim 9 further comprising:

a second structure on the substrate forming encapsulation;

a terminal pad with a portion of the first conductive pattern exposed through the first structure;

a component on the terminal pad; and

wherein:

the channel in the substrate forming encapsulation comprises:

the channel between the second structure and the first conductive pattern; and

the conductive material in the channel further comprises:

a second conductive pattern exposed through the second structure, and

an electrical via between the first conductive pattern and the second conductive pattern.

12. The system as claimed in claim 9 further comprising:

a component on the first conductive pattern;

a second integrated circuit die on the first integrated circuit die;

a second structure on the substrate forming encapsulation;

a terminal pad from a portion of the first conductive pattern exposed through the first structure; and

wherein:

the channel in the substrate forming encapsulation comprises:

the channel between the second structure and the first conductive pattern; and

the conductive material in the channel further comprises:

a second conductive pattern exposed through the second structure, and

an electrical via between the first conductive pattern and the second conductive pattern.

13. The system as claimed in claim 9 wherein:

the first conductive pattern on the first structure includes a contact;

the first integrated circuit die on the first conductive pattern is on the contact;

the substrate forming encapsulation to cover the first integrated circuit die and the first conductive pattern is a low coefficient of thermal expansion substrate forming encapsulation;

the channel in the substrate forming encapsulation is a connection channel; and

the conductive material in the channel is a metal or alloy.

14. The system as claimed in claim 13 wherein the first conductive pattern comprises:

the support on the first integrated circuit die;

a contact having the first integrated circuit die thereon; and

a trace to connect the first integrated circuit die.

15. The system as claimed in claim 13 wherein the conductive material in the channel includes a vertical shield in the substrate forming encapsulation.

16. The system as claimed in claim 13 further comprising:

a terminal pad with a portion of the first conductive pattern exposed; and

an external interconnect on the terminal pad.

17. The system as claimed in claim 13 further comprising:

a second structure on the substrate forming encapsulation;

wherein:

the conductive material in the channel further comprises:

a second conductive pattern exposed through the second structure; and

an external interconnect to the second conductive pattern.