Semiconductor device
View Patent ↗A semiconductor device includes a substrate having external connection terminals, and a semiconductor chip mounted over a semiconductor-chip mounting portion of the substrate. The external connection terminals are formed by sequentially forming an electroless nickel plating layer, an electroless gold plating layer, and an electrolytic gold plating layer on a terminal portion formed on a surface of the substrate.
1. A semiconductor device, comprising:
a first substrate having a first top surface, a first bottom surface opposite to the first top surface, a first external connection terminal, at least two second external connection terminals, a first wiring pattern, and a second wiring pattern; and
a first semiconductor chip provided on the first top surface;
wherein the first top surface comprises a chip area in the middle of the first top surface and a peripheral area outside the chip area, and said chip area and said peripheral area do not overlap with one another,
the first semiconductor chip is disposed in the chip area,
the first external connection terminal is formed in the peripheral area,
the at least two second external connection terminals are formed in the peripheral area outside the first external connection terminal,
the first wiring pattern extends from the first external connection terminal to an outer periphery of the first top surface,
the second wiring pattern extends from each of the at least two second external connection terminals to the outer periphery of the first top surface, and
the first wiring pattern passes through a place between adjacent ones of the at least two second external connection terminals.
2. The semiconductor device according to claim 1 , wherein multiple ones of the first external connection terminal and the at least two second external connection terminals are disposed in a grid array.
3. The semiconductor device according to claim 1 , wherein the first wiring pattern is an electroplating wiring pattern.
4. The semiconductor device according to claim 3 , wherein the second wiring pattern is an electroplating wiring pattern.
5. The semiconductor device according to claim 1 , wherein the first wiring pattern is a Cu wiring pattern.
6. The semiconductor device according to claim 5 , wherein the second wiring pattern is a Cu wiring pattern.
7. The semiconductor device according to claim 1 , wherein the first wiring pattern and the second wiring pattern are covered with a solder resist.
8. The semiconductor device according to claim 1 , wherein
the first external connection terminal has a plurality of layers, and
the plurality of the layers include an electroplating layer.
9. The semiconductor device according to claim 8 , wherein the plurality of the layers further include a first electroless plating layer formed on the first wiring pattern.
10. The semiconductor device according to claim 9 , wherein the plurality of the layers further include a second electroless plating layer formed on the first electroless plating layer.
11. The semiconductor device according to claim 10 , wherein the electroplating layer is formed on the second electroless plating layer.
12. The semiconductor device according to claim 1 , wherein a third external connection terminal is formed on the first bottom surface.
13. The semiconductor device according to claim 12 , wherein at least two fourth external connection terminals are formed outside the third external connection terminal on the first bottom surface.
14. The semiconductor device according to claim 13 , wherein
a third wiring pattern extends from the third external connection terminal to an outer periphery of the first bottom surface, and
the third wiring pattern passes through a place between adjacent ones of the at least two fourth external connection terminals.
15. The semiconductor device according to claim 1 , further comprising
a second substrate having a second top surface and a second bottom surface opposite to the second top surface, wherein
a fifth external connection terminal is formed on the second bottom surface, and
the first external connection terminal is connected to the fifth external connection terminal through a connection bump.
16. The semiconductor device according to claim 15 , further comprising a second semiconductor chip provided on the second top surface.
17. The semiconductor device according to claim 1 , wherein
the first top surface has a plurality of external connection terminals including the first external connection terminal and the at least two second external connection terminals,
the plurality of external connection terminals are disposed in the peripheral area, and
the plurality of external connection terminals are disposed at substantially equal intervals.
18. The semiconductor device according to claim 1 , further comprising a plurality of chip connection terminals connected to the first semiconductor chip, wherein
the plurality of chip connection terminals are disposed in the chip area.
19. The semiconductor device according to claim 18 , wherein a size of the first external connection terminal is larger than a size of one of the plurality of chip connection terminals.
20. The semiconductor device according to claim 18 , wherein a pitch of the plurality of chip connection terminals is narrower than a pitch of the at least two second external connection terminals.