IP Library › Granted Patent US 8,099,540
Granted Patent B2
US 8,099,540 · App. 11/545,477 · Granted Jan 17, 2012

Reconfigurable circuit

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Quick Facts
Patent No.
US 8,099,540
App. No.
11/545,477
Filed
Oct 11, 2006
Granted
Jan 17, 2012
Kind
B2
Art Unit
2111
USPC
710/317
Abstract

A reconfigurable circuit includes a network circuit for controlling connections between the output terminal and the input terminal of an arithmetic unit group, and a first selector connected between the arithmetic unit group and the network circuit. When a first control signal is in a first state, the first selector connects a first terminal of the arithmetic unit group to a first terminal of the network circuit, and also connects a second terminal of the arithmetic unit group to a second terminal of the network circuit. Meanwhile, when the first control signal is in a second state, the first selector connects the first terminal of the arithmetic unit group to the second terminal of the network circuit, and also connects the second terminal of the arithmetic unit group to the first terminal of the network circuit.

Claims (57)

1. A reconfigurable circuit comprising:

an arithmetic unit group including a first output terminal and a second output terminal, and performing arithmetic operations;

a network circuit including a first input terminal, a second input terminal and a switch, and switching connections between output terminals and input terminals of said arithmetic unit group by the switch; and

a first selector connected between said arithmetic unit group and the network circuit,

wherein the output terminals of said arithmetic unit group are connected to input terminals of said first selector,

output terminals of said first selector are connected to input terminals of said network circuit, and

output terminals of said net work circuit are connected to the input terminals of said arithmetic unit group, and

wherein when a first control signal is in a first state, said first selector connects said first output terminal of the arithmetic unit group to said first input terminal of the network circuit, and also connects said second output terminal of the arithmetic unit group to said second input terminal of the network circuit, while when the first control signal is in a second state, said first selector connects said first output terminal of the arithmetic unit group to said second input terminal of the network circuit, and also connects said second output terminal of the arithmetic unit group to said first input terminal of the network circuit.

2. The reconfigurable circuit according to claim 1 ,

wherein said arithmetic unit group further comprises a third output terminal and a fourth output terminal, and

said network circuit further comprises a third input terminal and a fourth input terminal, and

when a second control signal is in a first state, said first selector connects said third output terminal of the arithmetic unit group to said third input terminal of the network circuit, and also connects said fourth output terminal of the arithmetic unit group to said fourth input terminal of the network circuit, while when the second control signal is in a second state, said first selector connects said third output terminal of the arithmetic unit group to said fourth input terminal of the network circuit, and also connects said fourth output terminal of the arithmetic unit group to said third input terminal of the network circuit.

3. The reconfigurable circuit according to claim 1 , further comprising:

a network memory storing network control signal information; and

a register storing first control signal information,

wherein said network circuit controls said connection according to the network control signal information stored in said network memory, and

said first selector performs said connection according to the first control signal information stored in said register.

4. A reconfigurable circuit comprising:

an arithmetic unit group including a first input terminal and a second input terminal, and performing arithmetic operations;

a network circuit including a first output terminal, a second output terminal and a switch, and switching connections between output terminals and input terminals of said arithmetic unit group by the switch; and

a first selector connected between said arithmetic unit group and the network circuit,

wherein the output terminals of said arithmetic unit group are connected to an input terminals of said network circuit,

output terminals of said network circuit are connected to input terminals of said first selector, and

output terminals of said first selector are connected to the input terminals of said arithmetic unit group, and

wherein when the first control signal is in the first state, said first selector connects said first input terminal of the arithmetic unit group to said first output terminal of the network circuit, and also connects said second input terminal of the arithmetic unit group to said second output terminal of the network circuit, while when the first control signal is in the second state, said first selector connects said first input terminal of the arithmetic unit group to said second output terminal of the network circuit, and also connects said second input terminal of the arithmetic unit group to said first output terminal of the network circuit.

5. The reconfigurable circuit according to claim 4 ,

wherein said arithmetic unit group further comprises a third input terminal and a fourth input terminal, and

said network circuit further comprises a third output terminal and a fourth output terminal, and

when a second control signal is in a first state, said first selector connects said third input terminal of the arithmetic unit group to said third output terminal of the network circuit, and also connects said fourth input terminal of the arithmetic unit group to said fourth output terminal of the network circuit, while when a second control signal is in a second state, said first selector connects said third input terminal of the arithmetic unit group to said fourth output terminal of the network circuit, and also connects said fourth input terminal of the arithmetic unit group to said third output terminal of the network circuit.

6. The reconfigurable circuit according to claim 4 , further comprising:

a network memory storing network control signal information; and

a register storing first control signal information,

wherein said network circuit controls said connection according to the network control signal information stored in said network memory, and

said first selector performs said connection according to the first control signal information stored in said register.

7. A reconfigurable circuit comprising:

an arithmetic unit group including a first input terminal, a second input terminal, a first output terminal and a second output terminal, and performing arithmetic operations;

a network circuit including a first input terminal, a second input terminal, a first output terminal, a second output terminal and a switch, and switching connections between output terminals and input terminals of said arithmetic unit group by the switch;

a first selector connected between said arithmetic unit group and the network circuit; and

a second selector connected between said arithmetic unit group and the network circuit,

wherein the output terminals of said arithmetic unit group are connected to input terminals of said first selector,

output terminals of said first selector are connected to input terminals of said network circuit,

output terminals of said network circuit are connected to input terminals of said second selector, and

output terminals of said second selector are connected to the input terminals of said arithmetic unit group, and

wherein when the first control signal is in the first state, said first selector connects said first output terminal of the arithmetic unit group to said first input terminal of the network circuit, and also connects said second output terminal of the arithmetic unit group to said second input terminal of the network circuit, while when the first control signal is in the second state, said first selector connects said first output terminal of the arithmetic unit group to said second input terminal of the network circuit, and also connects said second output terminal of the arithmetic unit group to said first input terminal of the network circuit, and

wherein when a second control signal is in a first state, said second selector connects said first input terminal of the arithmetic unit group to said first output terminal of the network circuit, and also connects said second input terminal of the arithmetic unit group to said second output terminal of the network circuit, while when the second control signal is in a second state, said second selector connects said first input terminal of the arithmetic unit group to said second output terminal of the network circuit, and also connects said second input terminal of the arithmetic unit group to said first output terminal of the network circuit.

8. The reconfigurable circuit according to claim 7 ,

wherein said arithmetic unit group further comprises a third input terminal, a fourth input terminal, a third output terminal and a fourth output terminal, and

said network circuit further comprises a third input terminal, a fourth input terminal, a third output terminal and a fourth output terminal, and

when a third control signal is in a first state, said first selector connects said third output terminal of the arithmetic unit group to said third input terminal of the network circuit, and also connects said fourth output terminal of the arithmetic unit group to said fourth input terminal of the network circuit, while when the third control signal is in a second state, said first selector connects said third output terminal of the arithmetic unit group to said fourth input terminal of the network circuit, and also connects said fourth output terminal of the arithmetic unit group to said third input terminal of the network circuit, and wherein

when a fourth control signal is in a first state, said second selector connects said third input terminal of the arithmetic unit group to said third output terminal of the network circuit, and also connects said fourth input terminal of the arithmetic unit group to said fourth output terminal of the network circuit, while when the fourth control signal is in a second state, said second selector connects said third input terminal of the arithmetic unit group to said fourth output terminal of the network circuit, and also connects said fourth input terminal of the arithmetic unit group to said third output terminal of the network circuit.

9. The reconfigurable circuit according to claim 7 , further comprising:

a network memory storing network control signal information;

a first register storing first control signal information; and

a second register storing second control signal information,

wherein said network circuit controls said connection according to said network control signal information stored in said network memory, and

said first selector performs said connection according to said first control signal information stored in said first register, and

said second selector performs said connection according to said second control signal information stored in said second register.

Assignments (4)
MERGER Recorded Nov 14, 2025
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 073571/0456 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →