IP Library Granted Patent US 8,119,447
Granted Patent B2
US 8,119,447 · App. 12/486,271 · Granted Feb 21, 2012

Integrated circuit packaging system with through via die having pedestal and recess and method of manufacture thereof

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Quick Facts
Patent No.
US 8,119,447
App. No.
12/486,271
Filed
Jun 17, 2009
Granted
Feb 21, 2012
Kind
B2
Art Unit
2892
USPC
438/106
Abstract

A method of manufacture of an integrated circuit packaging system includes: providing a structure having a via filled with conductive material completely through the structure, a recess, and a pedestal portion bordering the recess; mounting a semiconductor device inside the recess in the structure; and encapsulating the structure and the semiconductor device in an encapsulation.

Claims (61)

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a substrate;

mounting a structure on the substrate, the structure having a via filled with conductive material completely through the structure, a recess, and a pedestal portion bordering the recess;

mounting a semiconductor device inside the recess of the structure and between the structure and the substrate; and

encapsulating the structure and the semiconductor device in an encapsulation.

2. The method as claimed in claim 1 further comprising:

forming a redistribution layer on a top surface of the structure.

3. The method as claimed in claim 1 further comprising:

mounting the semiconductor device and the structure to a substrate; and

connecting the semiconductor device and the structure to the substrate with internal interconnects.

4. The method as claimed in claim 1 wherein:

mounting the semiconductor device includes mounting a through via die, a wire-bonded die, a bumped die, a flip-chip, a semiconductor package, or a combination thereof.

5. The method as claimed in claim 1 wherein:

providing the structure having the via filled with conductive material includes providing the structure having the via filled with conductive material through the pedestal portion and not a body portion of the structure.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing a substrate;

providing a wafer;

forming a through hole, a blind hole, or a combination thereof in the wafer;

filling the through hole, the blind hole, or the combination thereof with a conductive filler;

forming a recess and a pedestal portion in the wafer by grinding or etching the structure;

singulating the wafer into a structure;

mounting the structure on the substrate;

mounting a semiconductor device inside the recess of the structure and between the structure and the substrate; and

encapsulating the structure and the semiconductor device in an encapsulation.

7. The method as claimed in claim 6 wherein:

forming the recess and the pedestal portion includes forming a pedestal portion with an L-shaped layout, a U-shaped layout, a plurality layout, or a combination thereof.

8. The method as claimed in claim 6 further comprising:

mounting an external device above the structure.

9. The method as claimed in claim 6 further comprising:

forming embedded-solder-balls embedded in the encapsulation having a surface exposed from the encapsulation.

10. The method as claimed in claim 6 further comprising:

connecting the structure to an inner stacking module with internal interconnects;

connecting the structure and the inner stacking module to a substrate with interconnects; and

wherein:

encapsulating the structure also includes encapsulating the inner stacking module with the encapsulation.

11. An integrated circuit packaging system comprising:

a substrate;

a structure mounted on the substrate, the structure having a via filled with conductive material completely through the structure, a recess, and a pedestal portion bordering the recess;

a semiconductor device mounted inside the recess of the structure and between the structure and the substrate; and

an encapsulation encapsulating the structure and the semiconductor device.

12. The system as claimed in claim 11 further comprising:

a redistribution layer on a top surface of the structure.

13. The system as claimed in claim 11 further comprising:

the semiconductor device is attached to the structure with a wire-in-film adhesive.

14. The system as claimed in claim 11 wherein:

the semiconductor device is a through via die, a wire-bonded die, a bumped die, a flip-chip, a semiconductor package, or a combination thereof.

15. The system as claimed in claim 11 wherein:

the via filled with conductive material is through the pedestal portion and not a body portion of the structure.

16. The system as claimed in claim 11 further comprising:

a substrate mounted to the semiconductor device and the structure; and

internal interconnects which connect the semiconductor device and the structure to the substrate.

17. The system as claimed in claim 16 wherein:

the pedestal portion is an L-shaped layout, a U-shaped layout, a plurality layout, or a combination thereof.

18. The system as claimed in claim 16 further comprising:

an external device mounted above the structure.

19. The system as claimed in claim 16 further comprising:

embedded-solder-balls embedded in the encapsulation having a surface exposed from the encapsulation.

20. The system as claimed in claim 16 further comprising:

an inner stacking module, the inner stacking module connected to the structure and both the inner stacking module and the structure connected to the substrate; and

wherein:

the inner stacking module is encapsulated with the encapsulation.