Semiconductor device and method of forming no-flow underfill material around vertical interconnect structure

1. A method of making a semiconductor device, comprising:

providing a first sacrificial carrier;

forming a first conductive layer over the first sacrificial carrier;

forming a first solder bump over the first conductive layer;

depositing a no-flow underfill material over the first sacrificial carrier, first conductive layer, and first solder bump;

compressing a first semiconductor die or component into the no-flow underfill material to electrically contact the first conductive layer;

planarizing a first surface of the no-flow underfill material and first solder bump;

forming a first interconnect structure over the first surface of the no-flow underfill material, the first interconnect structure being electrically connected to the first solder bump;

mounting a second sacrificial carrier over the first interconnect structure;

removing the first sacrificial carrier;

forming a second interconnect structure over a second surface of the no-flow underfill material opposite the first interconnect structure, the second interconnect structure being electrically connected to the first solder bump, first interconnect structure, and first semiconductor die or component; and

removing the second sacrificial carrier.

2. The method of claim 1 , wherein forming the first or second interconnect structure includes:

planarizing the second surface of the no-flow underfill material;

forming a first insulating layer over the no-flow underfill material;

forming a second conductive layer over the first insulating layer, the second conductive layer being electrically connected to the first solder bump; and

forming a second solder bump over the second conductive layer.

3. The method of claim 1 , wherein the first or second interconnect structure includes an integrated passive device.

4. The method of claim 1 , further including:

stacking a plurality of semiconductor devices; and

electrically connecting the semiconductor devices through the first and second interconnect structures and first solder bump.

5. The method of claim 1 , further including:

mounting a second semiconductor die over the first interconnect structure; and

electrically connecting the second semiconductor die to the first semiconductor die or component through the first and second interconnect structures and first solder bump.

6. A method of making a semiconductor device, comprising:

providing a first carrier;

forming a z-direction interconnect structure over the first carrier;

depositing a no-flow underfill material over the first carrier and z-direction interconnect structure;

compressing a first semiconductor die or component into the no-flow underfill material;

planarizing a first surface of the no-flow underfill material and z-direction interconnect structure; and

forming a first interconnect structure over the first surface of the no-flow underfill material, the first interconnect structure being electrically connected to the z-direction interconnect structure.

7. The method of claim 6 , further including:

mounting a second carrier over the first interconnect structure;

removing the first carrier;

forming a second interconnect structure over a second surface of the no-flow underfill material opposite the first interconnect structure, the second interconnect structure being electrically connected to the z-direction interconnect structure; and

removing the second carrier.

8. The method of claim 6 , wherein forming the first interconnect structure includes:

forming a first insulating layer over the no-flow underfill material; and

forming a second conductive layer over the first insulating layer, the second conductive layer being electrically connected to the z-direction interconnect structure.

9. The method of claim 6 , wherein the first interconnect structure includes an integrated passive device.

10. The method of claim 6 , further including:

stacking a plurality of semiconductor devices; and

electrically connecting the semiconductor devices through the z-direction interconnect structure.

11. The method of claim 6 , further including:

mounting a second semiconductor die over the first interconnect structure; and

electrically connecting the second semiconductor die to the first semiconductor die or component through the z-direction interconnect structure.

12. A method of making a semiconductor device, comprising:

providing a first carrier;

forming a z-direction interconnect structure over the first carrier, wherein the z-direction interconnect structure includes a solder bump;

depositing a no-flow underfill material over the first carrier and z-direction interconnect structure;

compressing a first semiconductor die or component into the no-flow underfill material; and

forming a first interconnect structure over the first surface of the no-flow underfill material, the first interconnect structure being electrically connected to the z-direction interconnect structure.

13. A method of making a semiconductor device, comprising:

providing a first carrier;

forming a z-direction interconnect structure over the first carrier;

depositing an encapsulant over the first carrier and z-direction interconnect structure;

compressing a first semiconductor die or component into the encapsulant;

planarizing a first surface of the encapsulant and z-direction interconnect structure;

forming a first interconnect structure over the first surface of the encapsulant, the first interconnect structure being electrically connected to the z-direction interconnect structure.

14. The method of claim 13 , wherein the encapsulant includes a no-flow underfill material.

15. The method of claim 13 , further including forming a second interconnect structure over a second surface of the encapsulant opposite the first interconnect structure, the second interconnect structure being electrically connected to the z-direction interconnect structure.

16. The method of claim 13 , wherein the z-direction interconnect structure includes a bump.

17. A method of making a semiconductor device, comprising:

providing a first carrier;

forming a z-direction interconnect structure over the first carrier;

depositing an encapsulant over the first carrier and z-direction interconnect structure;

compressing a first semiconductor die or component into the encapsulant;

forming a first interconnect structure over a first surface of the encapsulant, the first interconnect structure being electrically connected to the z-direction interconnect structure;

mounting a second carrier over the first interconnect structure;

removing the first carrier;

forming a second interconnect structure over a second surface of the encapsulant opposite the first interconnect structure, the second interconnect structure being electrically connected to the z-direction interconnect structure; and

removing the second carrier.

18. The method of claim, wherein the first interconnect structure includes an integrated passive device.

19. The method of claim 17 , further including:

stacking a plurality of semiconductor devices; and

electrically connecting the semiconductor devices through the z-direction interconnect structure.

20. The method of claim 17 , further including planarizing the first surface of the encapsulant and z-direction interconnect structure.

21. The method of claim 17 , wherein the z-direction interconnect structure includes a bump.

22. A method of making a semiconductor device, comprising:

providing a first carrier;

forming a z-direction interconnect structure over the first carrier, wherein the z-direction interconnect structure includes a solder bump;

depositing an encapsulant over the first carrier and z-direction interconnect structure;

compressing a first semiconductor die or component into the encapsulant; and

forming a first interconnect structure over a first surface of the encapsulant, the first interconnect structure being electrically connected to the z-direction interconnect structure.

23. The method of claim 22 , wherein the encapsulant includes a no-flow underfill material.

24. The method of claim 22 , further including planarizing the first surface of the encapsulant and z-direction interconnect structure.

25. The method of claim 22 , further including forming a second interconnect structure over a second side of the encapsulant opposite the first interconnect structure, the second interconnect structure being electrically connected to the z-direction interconnect structure.

26. The method of claim 22 , wherein the first interconnect structure includes an integrated passive device.

27. A method of making a semiconductor device, comprising:

providing a first carrier;

forming a z-direction interconnect structure over the first carrier;

depositing an encapsulant over the first carrier and around the z-direction interconnect structure such that an upper surface of the z-direction interconnect structure is exposed;

embedding a first semiconductor die or component in the encapsulant such that an upper surface of the semiconductor die is disposed above the encapsulant; and

forming a first interconnect structure over a first surface of the encapsulant, the first interconnect structure being electrically connected to the z-direction interconnect structure.

28. The method of claim 27 , wherein the encapsulant includes a no-flow underfill material.

29. The method of claim 27 , further including planarizing a surface of the encapsulant and z-direction interconnect structure.

30. The method of claim 27 , further including forming a second interconnect structure over a second side of the encapsulant opposite the first interconnect structure, the second interconnect structure being electrically connected to the z-direction interconnect structure.

31. The method of claim 27 , wherein the z-direction interconnect structure includes a bump.