IP Library Granted Patent US 8,283,226
Granted Patent B2
US 8,283,226 · App. 12/690,484 · Granted Oct 9, 2012

Method for manufacturing semiconductor device

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Quick Facts
Patent No.
US 8,283,226
App. No.
12/690,484
Filed
Jan 20, 2010
Granted
Oct 9, 2012
Kind
B2
Examiner
PATEL, REEMA
Art Unit
2812
USPC
438/285
Abstract

A method of manufacturing a semiconductor device includes forming a first cap film over gate electrodes formed in a first active region and a second active region, etching the first cap film over the first active region, forming a second cap film over the gate electrodes formed in the first active region and the second active region, etching the second cap film over the first active region, etching the first active region using the gate electrodes to form concave portions in the first active region, and embedding a semiconductor material in the concave portions.

Claims (37)

1. A method of manufacturing a semiconductor device, the method comprising:

forming an insulating film in a semiconductor substrate to define a first active region and a second active region;

forming a first gate electrode and a second gate electrode in the first active region;

forming a third gate electrode and a fourth gate electrode in the second active region;

forming, over the semiconductor substrate, a first cap film covering the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode;

forming a first mask pattern covering the first cap film over the second active region;

etching the first cap film over the first active region using the first mask pattern as an etching mask;

after etching the first cap film, removing the first mask pattern;

after removing the first mask pattern, forming a second cap film over the semiconductor substrate;

forming a second mask pattern covering the second cap film over the second active region;

etching the second cap film over the first active region using the second mask pattern as an etching mask;

etching the first active region using the first gate electrode and the second gate electrode as masks to form a recess in the first active region;

embedding, in the recess, a semiconductor material having a first lattice constant different from a second lattice constant of the semiconductor substrate;

implanting an impurity into the second active region using the third gate electrode and the fourth gate electrode as masks; and

forming a third cap film over the second cap film by plasma enhanced chemical vapor deposition after forming the second cap film, and before forming the second mask pattern.

2. The method of manufacturing a semiconductor device according to claim 1 , wherein the semiconductor substrate includes a silicon crystal, the first active region is an n-type active region, the second active region is a p-type active region, and the semiconductor material includes Si and Ge.

3. The method of manufacturing a semiconductor device according to claim 1 , wherein the first cap film and the second cap film are formed by thermal chemical vapor deposition.

4. The method of manufacturing a semiconductor device according to claim 1 , further comprising:

forming sidewall spacers on side surfaces of the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode after forming the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode, and before forming the first cap film.

5. The method of manufacturing a semiconductor device according to claim 4 , further comprising:

forming a silicon film over the semiconductor material, removing the first cap film and the second cap film over the second active region, and forming a metal silicide film over the first active region and the second active region, after forming the semiconductor material.

6. The method of manufacturing a semiconductor device according to claim 1 , wherein a first thickness of the first cap film formed over the semiconductor substrate between the first gate electrode and the second gate electrode is smaller than a second thickness of the first cap film formed over the upper surface of the first gate electrode, and a third thickness of the second cap film over the semiconductor substrate between the first gate electrode and the second gate electrode is smaller than a fourth thickness of the second cap film formed over the upper surface of the first gate electrode.

7. A method of manufacturing a semiconductor device, the method comprising:

forming an insulating film in a semiconductor substrate to define a first active region and a second active region;

forming a first gate electrode in the first active region;

forming a second gate electrode in the second active region;

forming, over the semiconductor substrate, a first cap film covering the first gate electrode and the second gate electrode;

forming a first mask pattern covering the first cap film over the second active region;

etching the first cap film over the first active region using the first mask pattern as an etching mask;

after etching the first cap film, removing the first mask pattern;

after removing the first mask pattern, forming a second cap film over the semiconductor substrate;

forming a second mask pattern covering the second cap film over the second active region;

etching the second cap film over the first active region using the second mask pattern as an etching mask;

etching the semiconductor substrate using the first gate electrode as a mask to form concave portions in the first active region;

embedding, in the concave portions, a semiconductor material having a first lattice constant different from a second lattice constant of the semiconductor substrate;

implanting an impurity into the second active region using the second gate electrode as a mask; and

forming a third cap film over the second cap film by plasma enhanced chemical vapor deposition after forming the second cap film, and before forming the second mask pattern.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
MERGER Recorded May 24, 2023
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU LIMITED
Reel/Frame 064221/0545 →
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 21, 2010
From: FUKUDA, MASAHIRO; SHIMAMUNE, YOSUKE; KASE, YUKA
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 023823/0261 →