IP Library › Granted Patent US 8,283,718
Granted Patent B2
US 8,283,718 · App. 11/611,856 · Granted Oct 9, 2012

Integrated circuit system with metal and semi-conducting gate

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Quick Facts
Patent No.
US 8,283,718
App. No.
11/611,856
Filed
Dec 16, 2006
Granted
Oct 9, 2012
Kind
B2
Examiner
DOAN, NGA
Art Unit
2813
USPC
438/585
Abstract

A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.

Claims (19)

1. An integrated circuit system comprising:

a first semi-conducting layer over a substrate;

a spacer stack having a gap filler adjacent to the first semi-conducting layer and an inter-layer dielectric over the gap filler, the gap filler extending from the first semi-conducting layer to an adjacent second semi-conducting layer, substantially filling a bottom portion of a gap between the first semi-conducting layer and the adjacent second semi-conducting layer and preventing adverse contamination of the first semi-conducting layer and the adjacent second semi-conducting layer;

a transition layer having a recess over the first semi-conducting layer and adjacent to the spacer stack; and

a metal layer in the recess;

wherein the gap filler comprises a single first dielectric material and the inter-layer dielectric comprises a second dielectric material different from the single first dielectric material.

2. The system as claimed in claim 1 further comprising a charge trap layer over the substrate and below the first semi-conducting layer.

3. The system as claimed in claim 1 further comprising a first top surface of the transition layer substantially coplanar with a second top surface of the spacer stack.

4. The system as claimed in claim 1 wherein the transition layer is adjacent to the inter-layer dielectric.

5. The system as claimed in claim 1 further comprising an electronic system or a subsystem with the integrated circuit system.

6. The system as claimed in claim 1 wherein:

the first semi-conducting layer is a polysilicon layer over the substrate;

the spacer stack has the nitride gap filler adjacent to the first semi-conducting layer and an inter-layer dielectric over the gap filler;

the transition layer is a tungsten nitride layer having the recess over the first semi-conducting layer and adjacent to the spacer stack; and

the metal layer a tungsten layer in the recess.

7. The system as claimed in claim 6 wherein the polysilicon layer over the substrate includes a charge trap layer over the substrate and below the polysilicon layer with the nitride gap filler adjacent to the charge trap layer.

8. The system as claimed in claim 6 further comprising a first top surface of the tungsten layer, a second top surface of the spacer stack, and a third top surface the tungsten nitride layer substantially co-planar.

9. The system as claimed in claim 6 wherein the tungsten nitride layer has a conformal configuration with the polysilicon layer and with an extension of the spacer stack.

10. The system as claimed in claim 6 further comprising a gate stack with the tungsten layer over the polysilicon layer.