Solder bump with inner core pillar in semiconductor package
View Patent ↗A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between the substrate and an intermediate conductive layer. The intermediate conductive layer is in electrical contact with the contact pad. A copper inner core pillar is formed by plating over the intermediate conductive layer. The inner core pillar has a rectangular, cylindrical, toroidal, or hollow cylinder form factor. A solder bump is formed around the inner core pillar by plating solder material and reflowing the solder material to form the solder bump. A first barrier layer and wetting layer are formed between the inner core pillar and solder bump. The solder bump is in electrical contact with the intermediate conductive layer.
1. A method of making a semiconductor device, comprising:
providing a semiconductor wafer including a plurality of active or passive devices formed on the semiconductor wafer;
forming a first conductive layer over the semiconductor wafer electrically connected to the active or passive devices;
forming an insulating layer over the first conductive layer and semiconductor wafer;
removing a portion of the insulating layer to expose the first conductive layer;
forming a second conductive layer over the first conductive layer and insulating layer;
forming a third conductive layer over the second conductive layer;
forming a fourth conductive layer over the third conductive layer;
forming a single core pillar including a hollow interior region over the fourth conductive layer and centered over first conductive layer, the single core pillar including a width less than a width of the exposed first conductive layer;
forming a fifth conductive layer over the fourth conductive layer and single core pillar and within the hollow interior region;
forming a sixth conductive layer over the fifth conductive layer and single core pillar and within the hollow interior region; and
forming a bump material over the sixth conductive layer.
2. The method of claim 1 , further including reflowing the bump material to form a spherical bump.
3. The method of claim 2 , wherein the single core pillar extends into the spherical bump at least two-thirds of a height of the spherical bump.
4. The method of claim 2 , wherein the single core pillar has a width 40-60% of a width of a diameter of the spherical bump.
5. The method of claim 1 , wherein forming the single core pillar includes:
forming a photoresist layer;
forming an opening in the photoresist layer; and
depositing conductive material in the opening of the photoresist layer.
6. The method of claim 1 , wherein the single core pillar includes copper, nickel, or other conductive material.
7. A method of making a semiconductor device, comprising:
providing a semiconductor substrate;
forming a first conductive layer over the semiconductor substrate;
forming an insulating layer over the first conductive layer and semiconductor substrate;
removing a portion of the insulating layer to expose the first conductive layer;
forming an under bump metallization (UBM) layer over the first conductive layer;
forming a single core pillar including a hollow interior region over the UBM layer and centered over first conductive layer, the single core pillar including a width less than a width of the exposed first conductive layer and extending into the bump at least two-thirds of a height of the bump;
forming a second conductive layer over the UBM layer and single core pillar;
forming a third conductive layer over the second conductive layer; and
forming a bump over the third conductive layer.
8. The method of claim 7 , wherein forming the UBM layer includes:
forming a fourth conductive layer over the first conductive layer;
forming a fifth conductive layer over the fourth conductive layer; and
forming a sixth conductive layer over the fifth conductive layer.
9. The method of claim 7 , wherein the single core pillar has a width 40-60% of a width of a diameter of the bump.
10. The method of claim 7 , further including:
forming the second conductive layer into the hollow interior region of the single core pillar; and
forming the third conductive layer over the second conductive layer and into the hollow interior region of the single core pillar.
11. The method of claim 7 , wherein the single core pillar has a rectangular, cylindrical, or toroidal shape.
12. A method of making a semiconductor device, comprising:
providing a semiconductor substrate;
forming a first conductive layer over the semiconductor substrate;
forming an under bump metallization (UBM) layer over the first conductive layer;
forming a single core pillar including a hollow interior region over the UBM layer and centered over the first conductive layer, the single core pillar including a width less than a width of the first conductive layer;
conformally applying a second conductive layer over the UBM layer and single core pillar; and
forming a bump over the second conductive layer.
13. The method of claim 12 , wherein forming the UBM layer includes:
forming a third conductive layer over the first conductive layer;
forming a fourth conductive layer over the third conductive layer; and
forming a fifth conductive layer over the fourth conductive layer.
14. The method of claim 12 , wherein the single core pillar extends into the bump at least two-thirds of a height of the bump.
15. The method of claim 12 , wherein the single core pillar has a width 40-60% of a width of a diameter of the bump.
16. The method of claim 12 , further including conformally applying the second conductive layer over the single core pillar and into the hollow interior region.
17. The method of claim 12 , wherein the single core pillar has a rectangular, cylindrical, or toroidal shape.
18. A method of making a semiconductor device, comprising:
providing a semiconductor substrate;
forming a first conductive layer over the semiconductor substrate;
forming an under bump metallization (UBM) layer over the first conductive layer;
forming a core pillar over the UBM layer and first conductive layer, the core pillar including a width less than a width of the first conductive layer;
forming a barrier layer within a hollow interior region of the core pillar;
forming a wetting layer within the hollow interior region of the core pillar; and
forming a bump over the core pillar.
19. The method of claim 18 , wherein the core pillar extends into the bump at least two-thirds of a height of the bump.
20. The method of claim 18 , wherein the core pillar has a width 40-60% of a width of a diameter of the bump.
21. The method of claim 18 , wherein forming the UBM layer includes:
forming a fourth conductive layer over the first conductive layer;
forming a fifth conductive layer over the fourth conductive layer; and
forming a sixth conductive layer over the fifth conductive layer.