Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures
View Patent ↗A semiconductor wafer contains a substrate having a plurality of active devices formed thereon. An analog circuit is formed on the substrate. The analog circuit can be an inductor, metal-insulator-metal capacitor, or resistor. The inductor is made with copper. A through substrate via (TSV) is formed in the substrate. A conductive material is deposited in the TSV in electrical contact with the analog circuit. An under bump metallization layer is formed on a backside of the substrate in electrical contact with the TSV. A solder material is deposited on the UBM layer. The solder material is reflowed to form a solder bump. A wire bond is formed on a top surface of the substrate. A redistribution layer is formed between the TSV and UBM. The analog circuit electrically connects through the TSV to the solder bump on the back side of the substrate.
1. A semiconductor device, comprising:
a substrate;
a via formed through the substrate;
a first insulating layer formed over a first surface of the substrate;
a first conductive layer formed over the first insulating layer;
a resistive layer formed over the first conductive layer;
a second insulating layer formed over the resistive layer;
a third insulating layer formed over the first insulating layer and first conductive layer;
a second conductive layer formed over the second and third insulating layers and first conductive layer, the first and second conductive layers extending into the via to form a conductive via;
a fourth insulating layer formed over a second surface of the substrate opposite the first surface of the substrate; and
an under bump metallization (UBM) formed over the second surface of the substrate and electrically connected to the conductive via.
2. The semiconductor device of claim 1 , further including a third conductive layer formed over the fourth insulating layer between the conductive via and UBM.
3. The semiconductor device of claim 1 , wherein the first conductive layer, resistive layer, second insulating layer, and second conductive layer constitute a metal-insulator-metal capacitor.
4. The semiconductor device of claim 1 , wherein a portion of the second conductive layer is wound to operate as an inductor.
5. The semiconductor device of claim 1 , further including:
a fifth insulating layer formed over the third insulating layer and second conductive layer; and
an encapsulant deposited over the fifth insulating layer and substrate.
6. The semiconductor device of claim 5 , further including a semiconductor die mounted over the fifth insulating layer and covered by the encapsulant and electrically connected to the second conductive layer.
7. A semiconductor device, comprising:
a substrate;
a via formed partially through the substrate to a depth less than a thickness of the substrate;
a conductive material deposited into the via to form a conductive via;
a first conductive layer formed over a first surface of the substrate, the first conductive layer extending into the via and electrically connected to the conductive via;
an integrated passive device (IPD) formed over the first surface of the substrate and electrically connected through the first conductive layer to the conductive via;
an under bump metallization (UBM) layer formed over a second surface of the substrate and electrically connected to the conductive via; and
a bump formed over the UBM layer.
8. The semiconductor device of claim 7 , further including:
a first insulating layer formed over the first surface of the substrate and extending into the via;
a second conductive layer formed over the first insulating layers; and
a second insulating layer formed over the second conductive layer.
9. The semiconductor device of claim 7 , further including a second conductive layer formed over the first conductive layer, wherein a portion of the second conductive layer is wound to operate as an inductor.
10. The semiconductor device of claim 7 , further including an encapsulant deposited over the substrate.
11. The semiconductor device of claim 7 , further including a semiconductor die mounted over the substrate.
12. The semiconductor device of claim 7 , wherein the bumps are laterally offset with respect to the conductive via.
13. A semiconductor device, comprising:
a substrate;
a first conductive layer formed over a first surface of the substrate;
a conductive via formed through the substrate and electrically common with the first conductive layer;
a first insulating layer formed over the first conductive layer;
a second insulating layer formed over the substrate and first conductive layer;
a second conductive layer formed over the first and second insulating layers and first conductive layer;
an under bump metallization (UBM) formed over a second surface of the substrate and electrically connected to the conductive via;
a third insulating layer formed over the second insulating layer and second conductive layer; and
an encapsulant deposited over the third insulating layer and substrate.
14. The semiconductor device of claim 13 , further including a semiconductor die mounted over the third insulating layer and covered by the encapsulant and electrically connected to the second conductive layer.
15. A semiconductor device, comprising:
a substrate;
an interconnect structure formed partially through a first surface of the substrate to a depth less than a thickness of the substrate;
an integrated passive device (IPD) formed over the substrate and electrically connected to the interconnect structure; and
an under bump metallization (UBM) layer formed over a second surface of the substrate and electrically connected to the interconnect structure.
16. The semiconductor device of claim 15 , wherein the IPD includes:
a first conductive layer formed over the first surface of the substrate;
an insulating layer formed over the first conductive layer; and
a second conductive layer formed over the insulating layer.
17. The semiconductor device of claim 15 , further including:
an insulating layer formed over the second surface of the substrate; and
a redistribution layer formed over the insulating layer between the interconnect structure and UBM layer.
18. The semiconductor device of claim 15 , wherein the IPD includes a resistor, capacitor, or inductor.
19. The semiconductor device of claim 15 , further including a bump formed over the UBM layer.
20. A semiconductor device, comprising:
a substrate having first and second surfaces;
a conductive via formed partially through the substrate to a depth less than a thickness of the substrate;
a first conductive layer formed over the first surface of the substrate and electrically connected to the conductive via; and
an electronic component mounted over the first surface of the substrate and electrically connected to the first conductive layer.
21. The semiconductor device of claim 20 , further including:
an under bump metallization (UBM) layer formed over the second surface of the substrate and electrically connected to the conductive via; and
a bump formed over the UBM layer.
22. The semiconductor device of claim 20 , further including:
a first insulating layer formed over the first surface of the substrate and extending into the via;
a second conductive layer formed over the first insulating layers; and
a second insulating layer formed over the second conductive layer.
23. The semiconductor device of claim 20 , further including a second conductive layer formed over the first conductive layer, wherein a portion of the second conductive layer is wound to operate as an inductor.
24. The semiconductor device of claim 20 , further including an encapsulant deposited over the substrate.
25. The semiconductor device of claim 20 , further including a semiconductor die mounted over the substrate.
26. The semiconductor device of claim 20 , wherein the bumps are laterally offset with respect to the conductive via.