Method and apparatus of minimizing extrinsic parasitic resistance in 60 GHz power amplifier circuits
View Patent ↗Very high frequency circuits suffer from parasitic resistances. At 60 GHz, conventional layout techniques can introduce loss into the circuit at critical locations. One critical interconnect between the output of a pre-driver and the gate of the final output stage causes 1 or 2 dB of loss due to the layout. By minimizing the number of via contacts, this conventional loss can be recovered using this new layout technique. In addition, a tap point of a via stack is used to modify the resonant characteristics of the interconnect. Finally, cross coupled devices in a resonant circuit are used to reduce the common mode noise at the expense of the common mode gain.
1. A transmitter comprising:
a first inductor formed in an upper metal layer of a die;
a drain of a first device coupled to said first inductor using a via stack,
a tap point of said via stack selected to maximize inductance placed in series with said first inductor and minimize resistance placed in series between a load and said drain;
said tap point tapped to a different metal layer; and
said different metal layer coupled to said load; whereby
said transmitter is improved in performance.
2. The transmitter of claim 1 , whereby
said load corresponds to a capacitance of a gate of a second device.
3. The transmitter of claim 2 , whereby
said first device has a first width,
said second device has a second width.
4. The transmitter of claim 3 , whereby
said second width is more than five times greater than said first width.
5. The transmitter of claim 1 , further comprising:
a parasitic capacitance associated with said first inductor, said drain and a second inductor associated with said via stack.
6. The transmitter of claim 5 , whereby
said parasitic capacitance and said inductors form a resonant circuit.
7. The transmitter of claim 1 , whereby
said different metal layer is a lower metal layer.
8. The transmitter of claim 1 , whereby
said performance is selected from said group consisting of gain, power delivery and resonant tuning.
9. A method of improving performance in a transmitter comprising the steps of:
forming a first inductor in an upper metal layer of a die;
coupling a drain of a device to said first, inductor using a via stack;
selecting a tap point of said via stack to maximize inductance placed in series with said first inductor and minimize resistance placed in series between a load and said drain;
tapping into said tap point with a different metal layer; and
coupling said different metal layer to said load; thereby
improving performance in said transmitter.
10. The method of claim 9 , further comprising the steps of
associating a parasitic capacitance with said first inductor, said drain and a second inductor associated with said via stack.
11. The method of claim 10 , whereby
said parasitic capacitance and said inductors form a resonant circuit.
12. The method of claim 9 , whereby
said load corresponds to a capacitance of a gate of a second device.
13. The method of claim 12 , whereby
said device has a first width,
said second device has a second width.
14. The method of claim 13 , whereby
said second width is more than five times greater than said first width.
15. The method of claim 9 , whereby
said different metal layer is a lower metal layer.
16. The method of claim 9 , whereby
said performance is selected from said group consisting of gain, power delivery and resonant tuning.
17. A method of tuning a resonant circuit in a transmitter comprising the steps of:
forming a first inductor in an upper metal layer of a die;
coupling a drain of a device to said first inductor using a via stack;
selecting a tap point of said via stack to vary inductance placed in series with said first inductor to tune said resonant circuit;
forming said resonant circuit with said first inductor and a second inductor associated with said via stack which is placed in series with said first inductor and said tap point;
tapping into said tap point with a different metal layer; and
coupling said different metal layer to a load; thereby
tuning said resonant circuit in said transmitter.
18. The method of claim 17 , whereby
said load corresponds to a capacitance of a gate of a second device.
19. The method of claim 17 , further comprising the steps of:
associating a parasitic capacitance with said first inductor, said drain and said second inductor associated with said via stack.
20. The method of claim 19 , whereby
said parasitic capacitance and said inductors form said resonant circuit.
21. An output stage comprising:
a first and a second device cross coupled to each other;
said first and second device having a first width are loaded with a portion of a resonant circuit;
a third device having a second width in parallel with said first device; and
a fourth device having said second width in parallel with said second device; whereby
said second width is at least five times said width of said first width.
22. The output stage of claim 21 , further comprising;
a ground (VSS) coupled to all sources of said devices; and
a power supply (VDD) coupled to said resonant circuit.
23. The output stage of claim 22 , further comprising;
a first inductor coupled between a drain of said first device and said power supply; and
a second inductor coupled between a drain of said second device and said power supply; whereby
said resonant circuit is formed by said first and second inductors.
24. The output stage of claim 23 , further comprising;
a third inductor magnetically coupled to said first and said second inductors.
25. The output stage of claim 24 , further comprising;
an antenna coupled to said third inductor.
26. The output stage of claim 21 , further comprising;
a first signal coupled to a gate of said third device; and
a second signal coupled to a gate of said fourth device; whereby
said first and second signals are formed by combining a differential and a common mode signal.
27. The output stage of claim 26 , whereby
a common mode noise is decreased in said output stage.