Driver circuit controlling threshold voltage shift of transistor
View Patent ↗Each shift register includes a first element controlled by a first potential node to supply a first driving voltage to an output terminal, a second element controlled by a second potential node to supply a second driving voltage lower than the first driving voltage to the output terminal, and a third element for controlling the first potential node and the second potential node so as to have opposite potential levels. Voltages are applied to the third element so that a state of A>B and A>C and a state of A<B and A<C, or a state of A>B and A<C and a state of A<B and A>C, or a state of A<B and A>C and a state of A>B and A<C are switched alternately (A: a gate terminal of the third element, B: a voltage applied to a first terminal thereof, C: a voltage applied to a second terminal thereof).
1. A display apparatus comprising:
a display panel including,
a plurality of video signal lines,
a plurality of scanning signal lines intersecting the video signal lines, and
a thin-film transistor which is formed near each intersection of the scanning signal lines and the video signal lines, where a pixel region is defined in a region surrounded by a pair of adjacent scanning signal lines and a pair of adjacent video signal lines; and
a scanning signal line driver circuit which is formed on the same board as the display panel so as to sequentially apply a select signal to the scanning signal lines,
wherein the scanning signal line driver circuit is connected to a plurality of shift registers that outputs an output signal, which is obtained by shifting a start pulse, as a start pulse of a next stage, each of the shift registers including,
a first element controlled by a first potential node to supply a first driving voltage to an output terminal,
a second element controlled by a second potential node to supply a second driving voltage lower than the first driving voltage to the output terminal, and
a third element for controlling the first potential node and the second potential node so as to have opposite potential levels, and
wherein when it is assumed that a voltage applied to a gate terminal of the third element is A, a voltage applied to a first terminal thereof is B, a voltage applied to a second terminal thereof is C, voltages are applied to the third element so that a state of A>B and A>C and a state of A<B and A<C, or a state of A>B and A<C and a state of A<B and A>C, or a state of A<B and A>C and a state of A>B and A<C are switched alternately.
2. The display apparatus according to claim 1 , wherein the second potential node is connected to a gate terminal of the second element, the first or second terminal of the third element is connected to the second potential node.
3. The display apparatus according to claim 1 , wherein gate terminals of the first and third elements are connected to the first potential node.
4. A display apparatus comprising:
a display panel including,
a plurality of video signal lines,
a plurality of scanning signal lines intersecting the video signal lines, and
a thin-film transistor which is formed near each intersection of the scanning signal lines and the video signal lines, where a pixel region is defined in a region surrounded by a pair of adjacent scanning signal lines and a pair of adjacent video signal lines; and
a scanning signal line driver circuit which is formed on the same board as the display panel so as to sequentially apply a select signal to the scanning signal lines,
wherein the scanning signal line driver circuit is connected to a plurality of shift registers that outputs an output signal, which is obtained by shifting a start pulse based on first and second clock signals, as a start pulse of a next stage, each of the shift registers including,
a first element controlled by a first potential node to supply a first driving voltage to an output terminal,
a second element controlled by a second potential node to supply a second driving voltage lower than the first driving voltage to the output terminal, and
a third element for controlling the first potential node and the second potential node so as to have opposite potential levels,
wherein one of first and second terminals of the third element is connected to the second potential node, and the other terminal is connected to an input terminal of the second clock signal, and
wherein the second clock signal is input to the other terminal.
5. The display apparatus according to claim 4 , wherein gate terminals of the first and third elements are connected to the first potential node.
6. The display apparatus according to claim 5 , wherein a gate terminal of the second element is connected to the second potential node.
7. A display apparatus comprising:
a display panel including,
a plurality of video signal lines,
a plurality of scanning signal lines intersecting the video signal lines, and
a thin-film transistor which is formed near each intersection of the scanning signal lines and the video signal lines, where a pixel region is defined in a region surrounded by a pair of adjacent scanning signal lines and a pair of adjacent video signal lines; and
a scanning signal line driver circuit which is formed on the same board as the display panel so as to sequentially apply a select signal to the scanning signal lines,
wherein the scanning signal line driver circuit is connected to a plurality of shift registers that outputs an output signal, which is obtained by shifting a start pulse based on first and second clock signals, as a start pulse of a next stage, each of the shift registers including,
a transistor element (T 5 ) controlled by a first potential node to supply a first driving voltage to an output terminal,
a transistor element (T 6 ) controlled by a second potential node to supply a second driving voltage lower than the first driving voltage to the output terminal,
a transistor element (T 4 ) for controlling the first potential node and the second potential node so as to have opposite potential levels,
a transistor element (T 3 ) for supplying a fixed high potential to the second potential node in response to an input of the first clock signal,
a transistor element (T 1 ) for supplying a fixed high potential to the first potential node in response to an input of the start pulse,
a transistor element (T 8 ) for supplying a fixed low potential to the first potential node in response to a shift output of a next stage,
a transistor element (T 2 ) controlled by the second potential node to supply a fixed low potential to the first potential node, and
a retention capacitor retaining the potential of the second potential node.
8. The display apparatus according to claim 7 , wherein an output period of the select signal is M line periods (where M is a natural number), and a high voltage of a select signal of a present stage is overlapped or is not overlapped with a high voltage of a select signal of a previous stage.