The gate electrode is formed above the polycrystalline semiconductor layer through the gate insulating film. The polycrystalline semiconductor layer includes a first region overlapping with the gate electrode in plan view. The first region is sandwiched between the second region and the third region. The second region of the polycrystalline semiconductor layer includes a first impurity diffusion region and two second impurity diffusion regions opposite in conductivity type to the first impurity diffusion region. The first region and the first impurity diffusion region are in contact with each other at a first boundary. The first region and the two second impurity diffusion regions are in contact with each other at second boundaries. The two second impurity diffusion regions sandwiching the first impurity diffusion region are provided along the gate electrode. Thus, a leak current is suppressed.
1. A display device, comprising:
an insulating substrate; and
a transistor which is provided above the insulating substrate and includes a polycrystalline semiconductor layer, a gate insulating film, and a gate electrode, wherein:
the gate electrode is formed above the polycrystalline semiconductor layer through the gate insulating film;
the polycrystalline semiconductor layer includes a first region overlapping with the gate electrode in plan view, a second region, and a third region;
the first region is sandwiched between the second region and the third region;
the second region of the polycrystalline semiconductor layer includes a first impurity diffusion region and two second impurity diffusion regions which are opposite in conductivity type to the first impurity diffusion region;
the first region and the first impurity diffusion region are in contact with each other at a first boundary;
the first region and the two second impurity diffusion regions are in contact with each other at second boundaries;
the two second impurity diffusion regions sandwiching the first impurity diffusion region are provided along the gate electrode;
the first and the second boundaries extend along a first edge of the gate electrode;
the third region of the polycrystalline semiconductor layer is of a same conductivity type as that of the first impurity diffusion region, the third region does not include a diffusion region which is of a same conductivity type as that of the second impurity diffusion regions;
the third region and the first region are in contact with each other at a third boundary;
the third boundary is extended along second edge of the gate electrode which is opposed to the first edge;
the first boundary is sandwiched between the two second boundaries;
the second boundaries are disposed at a respective outer side of the first boundary;
the second impurity diffusion regions extend along the first region a distance greater than a distance the second impurity diffusion regions extend along the first impurity diffusion region;
the second region forms a source region of the transistor; and
the third region forms a drain region of the transistor.
2. A display device according to claim 1 , wherein:
the transistor comprises a side transistor in which a leak current is generated when an off-voltage is applied to the gate electrode; and
each of the second boundaries has a length longer than a gate length of the side transistor.
3. A display device according to claim 1 , wherein
the transistor comprises a plurality of side transistors in which a leak current is generated when an off-voltage is applied to the gate electrode.
4. A display device according to claim 1 , further comprising
a first transistor whose first impurity diffusion layer conductivity type is an n-type and a second transistor whose first impurity diffusion layer conductivity type is a p-type, which are formed above the insulating substrate.
5. A display device according to claim 1 , further comprising
a complementary inverter circuit which is formed above the insulating substrate and includes a first transistor whose first impurity diffusion layer conductivity type is an n-type and a second transistor whose first impurity diffusion layer conductivity type is a p-type.
6. A display device according to claim 1 , further comprising
an analog switch circuit which is formed above the insulating substrate and includes a first transistor whose first impurity diffusion layer conductivity type is an n-type and a second transistor whose first impurity diffusion layer conductivity type is a p-type.
7. A display device according to claim 1 , further comprising
a plurality of scanning signal lines, a plurality of video signal lines, a plurality of switching elements, a plurality of pixel electrodes, and an integrated circuit including the transistor, which are formed above the insulating substrate, wherein:
the plurality of switching elements and the plurality of pixel electrodes are arranged in matrix to form a display area; and
the integrated circuit is provided outside the display area.
8. A display device, comprising:
an insulating substrate; and
a TFT element which is provided above the insulating substrate and includes a semiconductor layer with a polycrystalline semiconductor, a gate insulating film, and a gate electrode, wherein:
the gate electrode three-dimensionally crosses the semiconductor layer;
the semiconductor layer includes at least one first region having a form overlapping with the gate electrode in plan view, a second region, and a third region;
the second region and the third region sandwich the first region and are in contact with the first region;
the second region includes a first impurity diffusion region serving as a source of the TFT element and a second impurity diffusion region which is opposite in conductivity type to the first impurity diffusion region;
the first region and the second region have a boundary therebetween and the boundary includes a first boundary at which the first region and the first impurity diffusion region are in contact with each other and two second boundaries at which the first region and the second impurity diffusion region are in contact with each other;
wherein the first and the second boundaries extend along an edge of the gate electrode,
wherein the two second boundaries sandwich the first boundary and are located closer to end portions of the semiconductor layer than the first boundary, and
wherein the second impurity diffusion regions extend along the first region a distance greater than a distance the second impurity diffusion regions extend along the first impurity diffusion region.
9. A display device according to claim 8 , wherein:
the TFT element comprises side transistors which are provided in the end portions of the semiconductor layer and in which a leak current is generated when an off-voltage is applied to the gate electrode; and
each of the two second boundaries has a length in an extension direction of the gate electrode crossing the semiconductor layer, which is longer than a gate length of the side transistors.
10. A display device according to claim 8 , wherein
one semiconductor layer of the TFT element formed above the insulating substrate includes a plurality of the first regions.
11. A display device according to claim 8 , further comprising
a first TFT element whose first impurity diffusion layer conductivity type is an n-type and a second TFT element whose first impurity diffusion layer conductivity type is a p-type, which are formed above the insulating substrate.
12. A display device according to claim 8 , further comprising
a complementary inverter circuit which is formed above the insulating substrate and includes a first TFT element whose first impurity diffusion layer conductivity type is an n-type and a second TFT element whose first impurity diffusion layer conductivity type is a p-type.
13. A display device according to claim 8 , further comprising
an analog switch circuit which is formed above the insulating substrate and includes a first TFT element whose first impurity diffusion layer conductivity type is an n-type and a second TFT element whose first impurity diffusion layer conductivity type is a p-type.
14. A display device according to claim 8 , further comprising:
a display area which is formed above the insulating substrate and includes a plurality of scanning signal lines, a plurality of video signal lines, a plurality of switching elements, and a plurality of pixel electrodes, which are arranged in matrix; and
an integrated circuit including the TFT element, which is formed outside the display area.
15. A display device according to claim 8 , further comprising:
a pixel electrode; and
a switching element having a MIS structure, which is connected to the pixel electrode, wherein
the pixel electrode and the switching element are formed above the insulating substrate.
16. The display device according to claim 1 , wherein the first boundary and, the second boundaries extend continuously along the edge of the gate electrode.
17. The display device according to claim 8 , wherein the first boundary and the second boundaries extend continuously along the edge of the gate electrode.