IP Library Granted Patent US 8,476,111
Granted Patent B2
US 8,476,111 · App. 13/162,513 · Granted Jul 2, 2013

Integrated circuit packaging system with intra substrate die and method of manufacture thereof

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Quick Facts
Patent No.
US 8,476,111
App. No.
13/162,513
Filed
Jun 16, 2011
Granted
Jul 2, 2013
Kind
B2
Examiner
CHU, CHRIS C
Art Unit
2815
USPC
438/109
Abstract

A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a through hole; mounting an integrated circuit in the through hole, the integrated circuit having an inactive side and a vertical side; connecting a first interconnect in direct contact with the integrated circuit and the substrate; applying a wire-in-film adhesive around and above the integrated circuit leaving a portion of the vertical side and the inactive side exposed and covering a portion of the first interconnect; and mounting a chip above the integrated circuit and in direct contact with the wire-in-film adhesive.

Claims (32)

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a substrate having a through hole;

mounting an integrated circuit in the through hole, the integrated circuit having an inactive side and a vertical side;

connecting a first interconnect in direct contact with the integrated circuit and the substrate;

applying a wire-in-film adhesive around and above the integrated circuit leaving a portion of the vertical side and the inactive side exposed and covering a portion of the first interconnect; and

mounting a chip above the integrated circuit and in direct contact with the wire-in-film adhesive.

2. The method as claimed in claim 1 wherein applying the wire-in-film adhesive includes pre-forming the wire-in-film adhesive to a thickness less than the thickness of the substrate.

3. The method as claimed in claim 1 wherein:

mounting the chip includes mounting a first chip; and

further comprising:

mounting a second chip above the integrated circuit and above the first chip with the second chip in vertical alignment with the first chip.

4. The method as claimed in claim 1 further comprising attaching a heat sink in direct contact with the inactive side of the integrated circuit.

5. The method as claimed in claim 1 further comprising attaching a passive component in direct contact with the substrate.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing a substrate having a through hole;

mounting the substrate to a coverlay tape;

mounting an integrated circuit in the through hole and to the coverlay tape, the integrated circuit having an inactive side and a vertical side;

connecting a bond wire in direct contact with the integrated circuit and the substrate;

applying a wire-in-film adhesive around and above the integrated circuit leaving a portion of the vertical side and the inactive side exposed and covering a portion of the bond wire;

mounting a chip above the integrated circuit and in direct contact with the wire-in-film adhesive;

encapsulating the chip with an encapsulation above the substrate; and

mounting external interconnects below the substrate.

7. The method as claimed in claim 6 wherein applying the wire-in-film adhesive includes pre-forming the wire-in-film adhesive to a thickness less than the thickness of the integrated circuit.

8. The method as claimed in claim 6 wherein:

mounting the chip includes mounting a first chip; and

further comprising:

mounting a second chip connected peripheral to the integrated circuit and directly to the first chip with solder bumps.

9. The method as claimed in claim 6 wherein mounting the first chip includes mounting a wire-bonded integrated circuit chip or a through silicon via chip.

10. The method as claimed in claim 6 wherein:

mounting the chip includes mounting a first chip; and

further comprising:

mounting a second chip horizontally offset from the first chip.