Semiconductor package with interposer
View Patent ↗The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment.
1. A semiconductor package comprising:
a substrate having a lower substrate segment including a first plurality of lower interconnect pads;
said substrate including an upper substrate segment having an upper width and including a first plurality of upper interconnect pads;
an interposer for electrically connecting at least some of said first plurality of lower interconnect pads to at least some of said first plurality of upper interconnect pads;
said interposer having an interposer width that is different from said upper width of said upper substrate segment.
2. The semiconductor package of claim 1 , wherein a second plurality of lower interconnect pads are configured for use as contact pads for receiving a lower semiconductor die.
3. The semiconductor package of claim 2 , further comprising said lower semiconductor die.
4. The semiconductor package of claim 1 , wherein said upper substrate segment includes upper contact pads for receiving an upper semiconductor die.
5. The semiconductor package of claim 4 , further comprising said upper semiconductor die.
6. The semiconductor package of claim 1 , wherein a minimum pad pitch of said upper substrate segment is different from a minimum pad pitch of said lower substrate segment.
7. The semiconductor package of claim 1 , wherein said interposer comprises silicon.
8. A semiconductor package comprising:
a substrate having a lower substrate segment including a first and a second plurality of lower interconnect pads;
said substrate including an upper substrate segment having an upper width and including a first and a second plurality of upper interconnect pads;
an interposer for electrically connecting at least some of said first and second plurality of lower interconnect pads to at least some of said first and second plurality of upper interconnect pads;
said interposer having an interposer width that is different from said upper width of said upper substrate segment.
9. The semiconductor package of claim 8 , wherein said second plurality of lower interconnect pads are configured for use as contact pads for receiving a lower semiconductor die.
10. The semiconductor package of claim 9 , further comprising said lower semiconductor die.
11. The semiconductor package of claim 8 , wherein said upper substrate segment includes upper contact pads for receiving an upper semiconductor die.
12. The semiconductor package of claim 11 , further comprising said upper semiconductor die.
13. The semiconductor package of claim 8 , wherein a minimum pad pitch of said upper substrate segment is different from a minimum pad pitch of said lower substrate segment.
14. The semiconductor package of claim 8 , wherein said interposer comprises silicon.
15. A semiconductor package comprising:
a contiguous substrate having a lower substrate segment including a first and a second plurality of lower interconnect pads;
said contiguous substrate also including an upper substrate segment having an upper width and including a first and a second plurality of upper interconnect pads;
an interposer including through-semiconductor vias (TSVs) for electrically connecting at least some of said first and second plurality of lower interconnect pads to at least some of said first and second plurality of upper interconnect pads;
said interposer having an interposer width that is different from said upper width of said upper substrate segment.
16. The semiconductor package of claim 15 , wherein said second plurality of lower interconnect pads are configured for use as contact pads for receiving a lower semiconductor die.
17. The semiconductor package of claim 16 , further comprising said lower semiconductor die.
18. The semiconductor package of claim 15 , wherein said upper substrate segment includes upper contact pads for receiving an upper semiconductor die.
19. The semiconductor package of claim 18 , further comprising said upper semiconductor die.
20. The semiconductor package of claim 15 , wherein a minimum pad pitch of said upper substrate segment is different from a minimum pad pitch of said lower substrate segment.