Low power scan flip-flop cell

1. A low power scan flip-flop cell operable in a functional mode and a scan mode, comprising:

a multiplexer for receiving a data input (D) signal and a scan input (SI) signal, and generating a first data signal depending on a scan enable (SE) signal;

a master latch, connected to the multiplexer, for receiving the first data signal and generating a first latch signal;

a scan slave latch, connected to the master latch, for receiving the first latch signal and generating a scan output (SO) signal; and

a data slave latch, connected to the master latch and receiving the first latch signal, for generating a Q output depending on the SE signal and the first latch signal, wherein the Q output is maintained at a predetermined level during the scan mode, and

wherein the data slave latch comprises:

a first tri-state inverter, a first normal inverter, a second tri-state inverter and a first transistor, wherein the first normal inverter and the second tri-state inverter are connected in a loop, and the first tri-state inverter and the first transistor are connected in series and disposed between a power supply node (VDD) and ground (VSS),

wherein the first tri-state inverter receives the first latch signal and generates a second data signal (/Q) at a first connection node connected to an input of the first normal inverter and an output of the second tri-state inverter, and wherein the Q output is generated at a second connection node connected to an output of the first normal inverter and an input of the second tri-state inverter, and

wherein the first and second tri-state inverters are controlled by a clock signal.

2. The flip-flop cell of claim 1 , further comprising a first logic gate having an output connected to a clock input of the data slave latch, wherein the first logic gate receives an inverted SE input signal and a clock (CLK) signal and generates a first control signal that is input to the clock input of the data slave latch so that the Q output is maintained at a previous level during the scan mode.

3. The flip-flop cell of claim 2 , wherein the first logic gate comprises an AND gate.

4. The flip-flop cell of claim 2 , further comprising an inverter connected to the Q output of the data slave latch for generating a QN output signal.

5. The flip-flop cell of claim 1 , wherein the first transistor has a drain connected to the first tri-state inverter, a source connected to VSS, and a gate controlled by an inverted SE signal.

6. The flip-flop cell of claim 1 , wherein the first transistor is an NMOSFET.

7. The flip-flop cell of claim 1 , wherein the data slave latch further comprises a second transistor coupled between the power supply (VDD) and the first connection node, wherein the second transistor has a gate controlled by the inverted SE signal, and wherein the Q output is maintained at a logic low during the scan mode.

8. The flip-flop cell of claim 7 , wherein the second transistor is a PMOSFET.

9. The flip-flop cell of claim 1 , wherein the master latch comprises a third tri-state inverter, a second normal inverter and a fourth tri-state inverter, wherein the second normal inverter and the fourth inverter are connected in a loop, the third tri-state inverter receives the first data signal and generates a third data signal at a third connection node located at the input of the second normal inverter and the output of fourth tri-state inverter, and wherein the first latch signal is generated at an output of the second normal inverter.

10. The flip-flop cell of claim 9 , wherein the third and fourth tri-state inverters are controlled by the clock signal.

11. The flip-flop cell of claim 9 , wherein the scan slave latch comprises:

a fifth tri-state inverter that receives the first latch signal;

a third normal inverter; and

a sixth tri-state inverter connected in a loop with the third normal inverter;

wherein an output of the fifth tri-state inverter is connected to a fourth connection node at the input of the third normal inverter and the output of the sixth tri-state inverter,

the SO signal is generated at a fifth connection node located at the output of the third normal inverter and the input of the sixth tri-state inverter, and

the fifth and sixth tri-state inverters are controlled by the clock signal.

12. The flip-flop cell of claim 11 , wherein the data slave latch comprises:

a first transmission gate that receives the first latch signal;

a fourth normal inverter having an input connected to an output of the first transmission gate; and

a seventh tri-state inverter connected in a loop with the fourth normal inverter,

wherein a sixth connection node is located between the input of the fourth normal inverter and the output of the seventh tri-state inverter, and a seventh connection node is located between the output of the fourth normal inverter and the input of the seventh tri-state inverter,

wherein the Q output is generated at the sixth connection node, and

wherein the first transmission gate is controlled by an inverted SE signal, and the seventh tri-state inverter is controlled by a clock signal and the SE signal.

13. The flip-flop cell of claim 12 , wherein the scan slave latch comprises:

a fifth normal inverter; and

an eighth tri-state inverter connected in a loop with the fifth normal inverter,

wherein an eighth connection node located between the input of the fifth normal inverter and the output of the eighth tri-state inverter receives the first latch signal,

wherein the SO signal is generated at a ninth node located at the output of the fifth normal inverter, and

wherein the eighth tri-state inverter is controlled by the clock signal.

14. The flip-flop cell of claim 13 , further comprising:

a ninth tri-state inverter connected between an input of the first transmission gate of the data slave latch and the output of the master latch, wherein the ninth tri-state inverter is controlled by the clock signal.

15. A low power scan flip-flop cell operable in a functional mode and a scan mode, comprising:

a multiplexer for receiving a data input (D) signal and a scan input (SI) signal, and generating a first data signal depending on a scan enable (SE) signal;

a master latch, connected to the multiplexer, for receiving the first data signal and generating a first latch signal;

a scan slave latch, connected to the master latch, for receiving the first latch signal and generating a scan output (SO) signal; and

a data slave latch, connected to the master latch and receiving the first latch signal, for generating a Q output, wherein the Q output is maintained at a predetermined level during the scan mode, and

wherein the data slave latch comprises:

a first tri-state inverter,

a first normal inverter,

a second tri-state inverter connected in a loop with the first normal inverter,

a first transistor connected in series with the first tri-state inverter between a power supply (VDD) and ground (VSS),

wherein the first tri-state inverter receives the first latch signal and generates a first control signal (qb) at a first connection node located between the output of the first tri-state inverter and the input of the first normal inverter,

wherein the Q output is generated at a second connection node located at the output of the first normal inverter and the input of the second tri-state inverter,

wherein the first and second tri-state inverters are controlled by a clock signal,

wherein the first transistor has a drain connected to the first tri-state inverter, a source connected to ground, and a gate controlled by an inverted SE signal,

wherein the master latch comprises,

a third tri-state inverter, a second normal inverter and a fourth tri-state inverter connected in a loop with the second normal inverter, wherein the third tri-state inverter receives the first data signal and generates a third data signal at a node located at the input of the second normal inverter and the output of the fourth tri-state inverter, and wherein the first latch signal is generated at the output of the second normal inverter, and

wherein the scan slave latch comprises,

a fifth tri-state inverter ( 46 ) that receives the first latch signal,

a third normal inverter, and

a sixth tri-state inverter connected in a loop with the third normal inverter,

wherein the output of the fifth tri-state inverter is connected to a node at the input of the third normal inverter and the output of the sixth tri-state inverter,

wherein the SO signal is generated at node located at the output of the third normal inverter and an input of the sixth tri-state inverter, and

wherein the fifth and sixth tri-state inverters are controlled by the clock signal.

16. The flip-flop cell of claim 15 , wherein the data slave latch further comprises a second transistor coupled between the power supply and the first connection node, wherein the second transistor has a gate controlled by the inverted SE signal, and wherein the Q output is maintained at a logic low during the scan mode.