IPS-type liquid crystal display device having improved capacitance between pixel electrode and counter electrode
View Patent ↗There is provided a liquid crystal display device that enables increasing the capacitance between a pixel electrode and a common electrode without bringing about a significant decrease in the pixel aperture ratio. An In-Plane Switching LCD device in which a drain signal is supplied from one drain signal line to two pixel columns is configured such that there is a section having no drain signal line between adjacent pixels and a source electrode which is connected to a pixel electrode of a thin-film transistor extends into a contiguous pixel region that does not serve as an effective pixel region to provide one electrode of a capacitive element. A common electrode is formed in each pixel and the one electrode of the capacitive element is laid overlapping the common electrode with an insulation film intervening therebetween.
1. A liquid crystal display device comprising:
a first substrate and a second substrate placed to sandwich a liquid crystal layer therebetween; and
pixels over a plane which faces the liquid crystal layer of the first substrate, each pixel including a first electrode and a second electrode placed over or under the first electrode with a first insulation film intervening therebetween, wherein one of the first and second electrodes serves as a pixel electrode which is supplied with an image signal and the other electrode serves as a common electrode,
wherein a plurality of pixels are disposed along a first direction and form a pixel row,
wherein a plurality of pixel rows are disposed along a second direction perpendicular to the first direction,
wherein each of the pixel rows includes a first pixel and a second pixel which are supplied with a gate signal by a first gate signal line and a second gate signal line, respectively, extending along the first direction, wherein the first pixel is connected to the first gate signal line and the second pixel is connected to the second gate signal line,
wherein a first drain signal line and a second drain signal line extending in the second direction are laid to sandwich the first pixel and the second pixel therebetween,
wherein the first pixel is configured such that an image signal from the first drain signal line is supplied to the pixel electrode via a first thin-film transistor which is driven by a signal from the first gate signal line and placed close to the first gate signal line,
wherein the second pixel is configured such that an image signal from the second drain signal line is supplied to the pixel electrode via a second thin-film transistor which is driven by a signal from the second gate signal line and placed close to the second gate signal line,
wherein a source electrode, which is electrically connected to the pixel electrode of the first thin-film transistor, includes an extension part extending into a region of the second pixel, close to the first gate signal line, the extension part being formed overlapping the common electrode formed in the second pixel, when viewed from a planar view, with a second insulation film intervening between the extension part and the common electrode, and
wherein a source electrode, which is electrically connected to the pixel electrode of the second thin-film transistor, includes an extension part extending into a region of the first pixel, close to the second gate signal line, the extension part being formed overlapping the common electrode formed in the first pixel, when viewed from a planar view, with the second insulation film intervening between the extension part and the common electrode, and
wherein the extension part of the source electrode of the first thin-film transistor of the first pixel is formed on the same layer as the source electrode of the first thin-film transistor but is formed on a different layer from the pixel electrode of the first pixel, and is configured to form a first capacitor with the common electrode in the second pixel,
wherein the common electrode overlapping with the extension part of the source electrode of the first thin-film transistor is configured to form a second capacitor with the pixel electrode of the second pixel,
wherein the extension part of the source electrode of the second thin-film transistor of the second pixel is formed on the same layer as the source electrode of the second thin-film transistor but is formed on a different layer from the pixel electrode of the second pixel, and is configured to form a third capacitor with the common electrode in the first pixel, and
wherein the common electrode overlapping with the extension part of the source electrode of the second thin-film transistor is configured to form a fourth capacitor with the pixel electrode of the first pixel.
2. The liquid crystal display device according to claim 1 , wherein the source electrode of the first thin-film transistor is equipped with a first pad that provides a contact with the pixel electrode of the first pixel, the first pad being adjacent to the first thin-film transistor and the first gate signal line, and the source electrode of the second thin-film transistor is equipped with a second pad that provides a contact with the pixel electrode of the second pixel, the second pad being adjacent to the second thin-film transistor and the second gate signal line.
3. The liquid crystal display device according to claim 2 , wherein the first pad is formed between the source electrode of the first thin-film transistor and the extension part of the source electrode extending into the region of the second pixel, close to the first gate signal line, and the second pad is formed between the source electrode of the second thin-film transistor and the extension part of the source electrode extending into the region of the first pixel, close to the second gate signal line.
4. The liquid crystal display device according to claim 1 ,
wherein a first light shielding film and a second light shielding film are formed on a plane, which faces the liquid crystal layer, of the second substrate, the first light shielding film covering at least the first gate signal line and the first thin-film transistor and the second light shielding film covering at least the second gate signal line and the second thin-film transistor, when viewed from a planar view,
wherein the extension part of the source electrode of the first thin-film transistor is formed, at least in part, overlapping the first light shielding film, and
wherein the extension part of the source electrode of the second thin-film transistor is formed, at least in part, overlapping the second light shielding film.