IP Library › Granted Patent US 8,957,509
Granted Patent B2
US 8,957,509 · App. 13/166,809 · Granted Feb 17, 2015

Integrated circuit packaging system with thermal emission and method of manufacture thereof

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Quick Facts
Patent No.
US 8,957,509
App. No.
13/166,809
Filed
Jun 23, 2011
Granted
Feb 17, 2015
Kind
B2
Art Unit
2812
USPC
257/675
Abstract

A method of manufacture of an integrated circuit packaging system includes: forming a lead array having an innermost space with an innermost lead having an inner lead profile different around an inner non-horizontal side of the innermost lead; forming a middle lead having a middle lead profile the same around a lead side of the middle lead; placing an integrated circuit in the innermost space adjacent to the innermost lead; and forming a package encapsulation over the integrated circuit, the innermost lead, and the middle lead.

Claims (23)

1. A method of manufacture of an integrated circuit packaging system comprising:

forming a lead array having an innermost space with an innermost lead having an inner lead profile different around an inner non-horizontal side of the innermost lead and a middle lead adjacent to the innermost lead;

placing an integrated circuit in the innermost space adjacent to the innermost lead, wherein the inner non-horizontal side is planar and facing the integrated circuit;

applying a sealing filler in a sealing space directly and only between the innermost lead and the integrated circuit, the sealing filler having a filler bottom side coplanar with a die bottom side of the integrated circuit before completely forming the innermost lead and the middle lead with the innermost lead between the sealing filler and the middle lead;

connecting an electrical interconnect to the integrated circuit and the middle lead; and

forming a package encapsulation over the integrated circuit, the innermost lead, and the middle lead, the package encapsulation partially in the sealing space and directly on the sealing filler in the sealing space and the electrical interconnect.

2. The method as claimed in claim 1 wherein forming the package encapsulation includes forming the package encapsulation partially exposing the integrated circuit and the sealing filler.

3. The method as claimed in claim 1 wherein forming the lead array includes forming a lead bottom side of the lead array coplanar with a die bottom side of the integrated circuit and a filler bottom side of the sealing filler with the lead bottom side, the die bottom side, and the filler bottom side exposed.

4. A method of manufacture of an integrated circuit packaging system comprising:

forming a lead array having an innermost space with an innermost lead having an inner lead profile different around an inner non-horizontal side of the innermost lead and a middle lead adjacent to the innermost lead;

placing an integrated circuit in the innermost space adjacent to the innermost lead, wherein the inner non-horizontal side is planar and facing the integrated circuit;

applying a sealing filler in a sealing space directly and only between the innermost lead and the integrated circuit, the sealing filler having a filler bottom side coplanar with a die bottom side of the integrated circuit before completely forming the innermost lead and the middle lead with the innermost lead between the sealing filler and the middle lead;

connecting an electrical interconnect to the integrated circuit and the middle lead;

connecting another of the electrical interconnect to the integrated circuit and the innermost lead; and

forming a package encapsulation over the integrated circuit, the innermost lead, and the middle lead, the package encapsulation partially in the sealing space and directly on the sealing filler in the sealing space and the electrical interconnect.

5. An integrated circuit packaging system comprising:

a lead array having an innermost space with an innermost lead having an inner lead profile different around an inner non-horizontal side of the innermost lead and a middle lead adjacent to the innermost lead;

an integrated circuit in the innermost space adjacent to the innermost lead, wherein the inner non-horizontal side is planar and facing the integrated circuit;

a sealing filler in a sealing space directly and only between the innermost lead and the integrated circuit, the sealing filler having a filler bottom side coplanar with a die bottom side of the integrated circuit with the innermost lead between the sealing filler and the middle lead;

an electrical interconnect connected to the integrated circuit and the middle lead; and

a package encapsulation over the integrated circuit, the innermost lead, and the middle lead, the package encapsulation partially in the sealing space and directly on the sealing filler in the sealing space and the electrical interconnect.

6. The system as claimed in claim 5 wherein the package encapsulation includes the package encapsulation partially exposing the integrated circuit and the sealing filler.

7. The system as claimed in claim 5 wherein the lead array includes a lead bottom side of the lead array coplanar with a die bottom side of the integrated circuit and a filler bottom side of the sealing filler with the lead bottom side, the die bottom side, and the filler bottom side exposed.