IP Library Granted Patent US 8,994,196
Granted Patent B2
US 8,994,196 · App. 13/005,666 · Granted Mar 31, 2015

System and method for directional grinding on backside of a semiconductor wafer

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,994,196
App. No.
13/005,666
Filed
Jan 13, 2011
Granted
Mar 31, 2015
Kind
B2
Art Unit
2811
USPC
257/797
Abstract

A semiconductor device includes a backing plate, a semiconductor wafer, and integrated devices. The semiconductor wafer includes a plurality of semiconductor die having edges oriented along a reference line, a front surface facing the backing plate, and a backside surface. The backside surface is formed opposite the front surface and includes linear grind marks oriented along the reference line and diagonal with respect to the edges of the plurality of semiconductor die. The linear grind marks are formed by a linear motion of an abrasive surface, such as by a cylinder or wheel having an abrasive surface, and in one embodiment are oriented at 45 degrees with respect to the reference line. The linear grind marks increase a strength of the plurality of semiconductor die to resist cracking. Integrated devices are formed on the front surface of the semiconductor wafer.

Claims (41)

1. A semiconductor device, comprising:

a semiconductor wafer including,

(a) a plurality of semiconductor die comprising edges oriented along a reference line,

(b) radial grind marks formed on a first surface of the semiconductor wafer to a first depth,

(c) linear grind marks formed on the first surface of the semiconductor wafer at an angle to the reference line to a second depth, and

(d) a semiconductor circuit formed on a second surface of the semiconductor wafer opposite the first surface of the semiconductor wafer.

2. The semiconductor device of claim 1 , wherein the linear grind marks are oriented 45 degrees with respect to the reference line.

3. The semiconductor device of claim 1 , wherein the linear grind marks are formed by a cylinder having an abrasive surface.

4. The semiconductor device of claim 1 , wherein the linear grind marks are formed by a wheel having an abrasive surface.

5. The semiconductor device of claim 1 , wherein the linear grind marks are oriented diagonal with respect to the reference line to increase a strength of the plurality of semiconductor die to resist cracking.

6. A semiconductor device, comprising:

a semiconductor wafer including,

(a) a plurality of semiconductor die,

(b) radial grind marks formed on a first surface of the semiconductor wafer to a first depth, and

(c) linear grind marks formed on the first surface of the semiconductor wafer to a second depth and diagonally with respect to edges of the plurality of semiconductor die.

7. The semiconductor device of claim 6 , wherein the semiconductor wafer is aligned with the edges of the plurality of semiconductor die oriented along a reference line.

8. The semiconductor device of claim 7 , wherein the linear grind marks are oriented 45 degrees with respect to the reference line.

9. The semiconductor device of claim 6 , wherein the linear grind marks are formed by a cylinder or wheel having an abrasive surface.

10. The semiconductor device of claim 6 , wherein the linear grind marks are formed by an abrasive surface having at least a 4000 mesh count.

11. The semiconductor device of claim 6 , wherein the linear grind marks are oriented diagonal with respect to the edges of the plurality of semiconductor die to increase a strength of the plurality of semiconductor die to resist cracking.

12. A semiconductor device, comprising:

a semiconductor wafer including,

(a) a semiconductor die,

(b) first grind marks formed on a surface of the semiconductor wafer to a first depth, and

(c) linear grind marks formed on the surface of the semiconductor wafer to a second depth and oriented diagonal to an edge of the semiconductor die.

13. The semiconductor device of claim 12 , wherein the semiconductor wafer is aligned with the edge of the semiconductor die oriented along a reference line.

14. The semiconductor device of claim 13 , wherein the linear grind marks are oriented 45 degrees with respect to the reference line.

15. The semiconductor device of claim 12 , wherein the linear grind marks are formed by a cylinder having an abrasive surface.

16. The semiconductor device of claim 12 , wherein the linear grind marks are formed by a wheel having an abrasive surface.

17. The semiconductor device of claim 12 , wherein the linear grind marks are formed by an abrasive surface having at least a 4000 mesh count.

18. The semiconductor wafer of claim 12 , wherein the linear grind marks are oriented diagonal with respect to the edge of the semiconductor die to increase a strength of the semiconductor die to resist cracking.

19. A semiconductor device, comprising:

a semiconductor die;

first grind marks formed on a surface of the semiconductor die; and

second grind marks formed on the surface of the semiconductor die and oriented diagonal to an edge of the semiconductor die.

20. The semiconductor device of claim 19 , wherein the semiconductor die is aligned with the edges of the semiconductor die oriented along a reference line.

21. The semiconductor device of claim 20 , wherein the second grind marks are oriented 45 degrees with respect to the reference line.

22. The semiconductor device of claim 19 , wherein the second grind marks are formed by a cylinder including an abrasive surface.

23. The semiconductor device of claim 19 , wherein the second grind marks are formed by a wheel including an abrasive surface.

24. The semiconductor device of claim 19 , wherein the second grind marks are formed with an abrasive surface including at least a 4000 mesh count.

25. The semiconductor device of claim 19 , wherein the second grind marks are oriented diagonal with respect to the edges of the semiconductor die to increase a strength of the semiconductor die to resist cracking.