On-chip probe circuit for detecting faults in an FPGA

1. An integrated circuit including:

a clock input;

a first output;

a second output;

a fixed delay element having an input coupled to the clock input and an output;

a programmable delay element having an input coupled to the clock input, an output, and at least one control input for receiving delay information;

a first multiplexer having a first data input coupled to the output of the fixed delay element, a second data input coupled to the output of the programmable delay element, an output coupled to the first output, and a control input; and

a second multiplexer having a first data input coupled to the output of the programmable delay element, a second data input coupled to the output of the fixed delay element, an output coupled to the second output, and a control input.

2. The integrated circuit of claim 1 , wherein:

the fixed delay element is coupled to the clock input through a programmable pulse counter having an input coupled to the clock input, an output, and at least one control input for receiving count information; and

the programmable delay element is coupled to the clock input through the programmable pulse counter.

3. The integrated circuit of claim 1 , further including an arrival order detector circuit coupled between the first output and the second output.

4. The integrated circuit of claim 3 , wherein the arrival order detector circuit includes:

a first flip-flop having a clock input coupled to the programmable delay element and a data input coupled to the fixed delay element; and

a second flip-flop having a clock input coupled to the fixed delay element and a data input coupled to the programmable delay element.

5. The integrated circuit of claim 4 further including a CLEAR signal line connected to a CLEAR input of the first flip-flop and a CLEAR input of the second flip-flop.

6. The integrated circuit of claim 4 further including a SET signal line connected to a SET input of the first flip-flop and a SET input of the second flip-flop.

7. The integrated circuit of claim 1 , further including:

a multicycle control input:

a down counter coupled to the clock input and having at least one control input to receive a control input specifying clock N pulses; and wherein:

the fixed delay element is coupled to the clock input through a first timing circuit responsive to signals from the down counter and the multicycle control input; and

the programmable delay element is coupled to the clock input through a second timing circuit responsive to signals from the down counter and the multicycle control input.

8. The integrated circuit of claim 7 wherein:

the first and second timing circuits simultaneously pass N clock pulses from the clock input to the fixed delay element and the programmable delay element when the multicycle control input is in a first logic state; and

the first timing circuit passes a first of N clock pulses from the clock input to the fixed delay element and the second timing circuit passes an (N+1)th clock pulse to the programmable delay element when the multicycle control input is in a second logic state opposite the first logic state.

9. The integrated circuit of claim 8 , further including:

an OR gate having a first input coupled to the fixed delay element, a second input coupled to the programmable delay element, and an output coupled to a third data input of the first multiplexer and a third data input of the second multiplexer.