IP Library › Granted Patent US 9,059,186
Granted Patent B2
US 9,059,186 · App. 14/154,049 · Granted Jun 16, 2015

Embedded semiconductor die package and method of making the same using metal frame carrier

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Quick Facts
Patent No.
US 9,059,186
App. No.
14/154,049
Filed
Jan 13, 2014
Granted
Jun 16, 2015
Kind
B2
Examiner
NHU, DAVID
Art Unit
2817
USPC
257/738
Abstract

An embedded semiconductor die package is made by mounting a frame carrier to a temporary carrier with an adhesive. The frame carrier includes die mounting sites each including a leadframe interconnect structure around a cavity. A semiconductor die is disposed in each cavity. An encapsulant is deposited in the cavity over the die. A package interconnect structure is formed over the leadframe interconnect structure and encapsulant. The package interconnect structure and leadframe interconnect structure are electrically connected to the die. The frame carrier is singulated into individual embedded die packages. The semiconductor die can be vertically stacked or placed side-by-side within the cavity. The embedded die packages can be stacked and electrically interconnected through the leadframe interconnect structure. A semiconductor device can be mounted to the embedded die package and electrically connected to the die through the leadframe interconnect structure.

Claims (41)

1. A method of making a semiconductor device, comprising:

providing a first interconnect structure;

disposing a first semiconductor die within a cavity of the first interconnect structure;

depositing an encapsulant over the first semiconductor die; and

forming a first conductive layer over the first semiconductor die and a first surface of the encapsulant.

2. The method of claim 1 , further including forming a second interconnect structure over a second surface of the encapsulant opposite the first surface of the encapsulant.

3. The method of claim 2 , wherein forming the second interconnect structure includes:

forming a second conductive layer over the second surface of the encapsulant; and

forming an insulating layer over the second conductive layer.

4. The method of claim 1 , wherein the first interconnect structure includes a conductive post and a lead finger extending from the conductive post.

5. The method of claim 1 , further including disposing a second semiconductor die within the cavity of the first interconnect structure.

6. The method of claim 1 , further including disposing a second semiconductor die over the first conductive layer.

7. A method of making a semiconductor device, comprising:

providing a first interconnect structure;

disposing a first semiconductor die within a cavity of the first interconnect structure; and

depositing an encapsulant over the first semiconductor die.

8. The method of claim 7 , further including forming a first conductive layer over the encapsulant.

9. The method of claim 7 , further including forming a second interconnect structure over the encapsulant.

10. The method of claim 9 , wherein forming the second interconnect structure includes:

forming a first conductive layer over the encapsulant;

forming an insulating layer over the first conductive layer; and

forming a second conductive layer over the insulating layer.

11. The method of claim 7 , further including disposing a second semiconductor die within the cavity of the first interconnect structure.

12. The method of claim 7 , further including removing a portion of the encapsulant to expose the first interconnect structure.

13. The method of claim 7 , wherein the first interconnect structure includes a conductive post and a lead finger extending from the conductive post.

14. A method of making a semiconductor device, comprising:

providing a first interconnect structure including a conductive post; and

disposing a first semiconductor die within a cavity of the first interconnect structure.

15. The method of claim 14 , further including depositing an encapsulant over the first semiconductor die.

16. The method of claim 15 , further including disposing a second interconnect structure in the encapsulant over a contact pad of the first semiconductor die.

17. The method of claim 14 , further including forming a first conductive layer over a first surface of the first semiconductor die.

18. The method of claim 17 , further including forming a second conductive layer over a second surface of the first semiconductor die opposite the first surface of the first semiconductor die, wherein the conductive post of the first interconnect structure electrically connects the first conductive layer and second conductive layer.

19. The method of claim 14 , further including disposing a second semiconductor die within the cavity of the first interconnect structure.

20. The method of claim 14 , wherein the first interconnect structure further includes a plurality of lead fingers extending from the conductive post.

21. A method of making a semiconductor device, comprising:

providing an interconnect structure; and

disposing a first semiconductor die within the interconnect structure.

22. The method of claim 21 , further including depositing an encapsulant over the first semiconductor die within a cavity of the interconnect structure.

23. The method of claim 22 , further including forming a conductive layer over the encapsulant electrically connecting the interconnect structure and first semiconductor die.

24. The method of claim 21 , further including disposing a second semiconductor die within the interconnect structure.

25. The method of claim 21 , further including disposing a second semiconductor die over the interconnect structure.