IP Library › Granted Patent US 9,082,780
Granted Patent B2
US 9,082,780 · App. 13/428,439 · Granted Jul 14, 2015

Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layer

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Quick Facts
Patent No.
US 9,082,780
App. No.
13/428,439
Filed
Mar 23, 2012
Granted
Jul 14, 2015
Kind
B2
Art Unit
2891
USPC
438/109
Abstract

A semiconductor device has a semiconductor die. An encapsulant is deposited around the semiconductor die. An interconnect structure having a conductive bump is formed over the encapsulant and semiconductor die. A mechanical support layer is formed over the interconnect structure and around the conductive bump. The mechanical support layer is formed over a corner of the semiconductor die and over a corner of the interconnect structure. An opening is formed through the encapsulant that extends to the interconnect structure. A conductive material is deposited within the opening to form a conductive through encapsulant via (TEV) that is electrically connected to the interconnect structure. A semiconductor device is mounted to the TEV and over the semiconductor die to form a package-on-package (PoP) device. A warpage balance layer is formed over the encapsulant opposite the interconnect structure.

Claims (56)

1. A method of making a semiconductor device, comprising:

providing a semiconductor die;

depositing an encapsulant around the semiconductor die;

forming an interconnect structure including a conductive bump over the encapsulant and semiconductor die;

forming a mechanical support layer over the interconnect structure and around the conductive bump;

forming an opening through the encapsulant that extends to the interconnect structure after forming the mechanical support layer; and

depositing conductive material within the opening to form a conductive through encapsulant via (TEV) coupled to the interconnect structure.

2. The method of claim 1 , further including disposing a semiconductor component over the TEV and over the semiconductor die to form a package-on-package device.

3. The method of claim 2 , further including forming flux around the conductive material within the opening.

4. The method of claim 1 , further including forming the mechanical support layer over a corner of the semiconductor die and over a corner of the interconnect structure.

5. The method of claim 1 , further including forming the mechanical support layer over a first portion of the interconnect structure outside a footprint of the semiconductor die such that a second portion of the interconnect structure within the footprint of the semiconductor die is devoid of the mechanical support layer.

6. The method of claim 1 , further including forming the mechanical support layer partially outside a footprint of the semiconductor die and partially within the footprint of the semiconductor die.

7. A method of making a semiconductor device, comprising:

providing a semiconductor die;

depositing an encapsulant around the semiconductor die;

forming an interconnect structure including a conductive bump over the encapsulant and semiconductor die;

forming a mechanical support layer over the interconnect structure and around the conductive bump; and

forming a through encapsulant via (TEV) through the encapsulant over the mechanical support layer.

8. The method of claim 7 , wherein forming the TEV further includes:

forming an opening through the encapsulant;

forming a conductive material within the opening; and

forming flux around the conductive material.

9. The method of claim 7 , further including forming the mechanical support layer over a corner of the semiconductor die and over a corner of the interconnect structure.

10. The method of claim 7 , further including forming the mechanical support layer over a first portion of the interconnect structure outside a footprint of the semiconductor die such that a second portion of the interconnect structure within the footprint of the semiconductor die is devoid of the mechanical support layer.

11. The method of claim 7 , further including forming the mechanical support layer partially outside a footprint of the semiconductor die and partially within the footprint of the semiconductor die.

12. The method of claim 7 , wherein forming the interconnect structure includes:

depositing a first insulating layer over the semiconductor die and over the encapsulant;

depositing a conductive layer over the first insulating layer;

depositing a second insulating layer over the conductive layer; and

forming the conductive bump over the second insulating layer and electrically connected to the conductive layer.

13. The method of claim 7 , further including forming a warpage balance layer over the encapsulant opposite the interconnect structure.

14. A method of making a semiconductor device, comprising:

providing a semiconductor die;

depositing an encapsulant around the semiconductor die;

forming an interconnect structure over the encapsulant and semiconductor die;

forming a mechanical support layer over the interconnect structure; and

forming an opening in the encapsulant over the mechanical support layer.

15. The method of claim 14 , further including depositing conductive material within the opening to form a through encapsulant via (TEV) electrically connected to the interconnect structure.

16. The method of claim 15 , further including disposing a semiconductor component over the TEV and over the semiconductor die to form a package-on-package device.

17. The method of claim 14 , further including forming the mechanical support layer over a corner of the semiconductor die and over a corner of the interconnect structure.

18. The method of claim 14 , further including forming the mechanical support layer over a first portion of the interconnect structure outside a footprint of the semiconductor die such that a second portion of the interconnect structure within the footprint of the semiconductor die is void of the mechanical support layer.

19. The method of claim 14 , further including forming the mechanical support layer partially outside a footprint of the semiconductor die and partially within the footprint of the semiconductor die.

20. The method of claim 14 , wherein forming the interconnect structure includes:

depositing a first insulating layer over the semiconductor die and over the encapsulant;

depositing a conductive layer over the first insulating layer;

depositing a second insulating layer over the conductive layer; and

forming a conductive bump over the second insulating layer and electrically connected to the conductive layer.

21. A method of making a semiconductor device, comprising:

providing a semiconductor die;

disposing an encapsulant around the semiconductor die;

forming a mechanical support layer over the encapsulant; and

forming a through encapsulant via (TEV) in the encapsulant over the mechanical support layer.

22. The method of claim 21 , further including forming the mechanical support layer over a corner of the semiconductor die and over a corner of the encapsulant.

23. The method of claim 21 , further including forming the mechanical support layer over a first portion of the encapsulant outside a footprint of the semiconductor die with a second portion of the encapsulant within the footprint of the semiconductor die being devoid of the mechanical support layer.

24. The method of claim 21 , further including forming the mechanical support layer partially outside a footprint of the semiconductor die and partially within the footprint of the semiconductor die.

25. The method of claim 21 , further including forming a warpage balance layer over the encapsulant opposite the encapsulant.