Stacked integrated circuit package system
View Patent ↗A stacked integrated circuit package system includes: providing a base integrated circuit package, and mounting a top integrated circuit package having a top interposer and a top encapsulation with a cavity therein or the cavity as a space between top intra-stack interconnects and the top interposer, with the top interposer exposed by the cavity, over the base integrated circuit package.
1. A method of manufacture of a stacked integrated circuit package system comprising:
providing a base integrated circuit package including:
providing a base package carrier,
mounting a base interposer over the base package carrier, the base interposer having a central aperture,
forming a base intra-stack interconnect on a top surface of the base interposer,
forming a base interposer interconnect on a bottom surface of the base interposer, and
mounting a flip chip within the central aperture and on the base package carrier; and
mounting a top integrated circuit package on the base intra-stack interconnect and over the base interposer, the top integrated circuit package including:
a top interposer,
a top package carrier below the top interposer and with the base intra-stack interconnect on a bottom surface of the top package carrier and with the flip chip in direct contact with the bottom surface of the top package carrier, and
a top encapsulation on the top package carrier and the top interposer with a recess therein with the top interposer exposed by the recess.
2. The method as claimed in claim 1 wherein mounting the flip chip includes mounting the flip chip over the base package carrier.
3. The method as claimed in claim 1 wherein mounting a top integrated circuit package includes:
mounting a first top integrated circuit device on the top interposer; and
mounting a second top integrated circuit device on the top package carrier.
4. The method as claimed in claim 1 wherein mounting the top integrated circuit package having the top encapsulation with the recess therein and the top interposer exposed by the recess includes providing the top package carrier with the recess over the top package carrier.
5. The method as claimed in claim 1 further comprising forming a base external interconnect below the base integrated circuit package.
6. A method of manufacture of a stacked integrated circuit package system comprising:
providing a base integrated circuit package including:
providing a base package carrier,
mounting a base interposer over the base package carrier, the base interposer having a central aperture,
forming a base intra-stack interconnect on a top surface of the base interposer,
forming a base interposer interconnect on a bottom surface of the base interposer, and
mounting a flip chip within the central aperture and on the base package carrier;
forming a base external interconnect below the base integrated circuit package; and
mounting a top integrated circuit package on the base intra-stack interconnect and over the base interposer, the top integrated circuit package including:
a top interposer,
a top package carrier below the top interposer and with the base intra-stack interconnect on a bottom surface of the top package carrier and with the flip chip in direct contact with the bottom surface of the top package carrier, and
a top encapsulation on the top package carrier and the top interposer with a recess therein with the top interposer exposed by the recess.
7. The method as claimed in claim 6 wherein:
forming the base intra-stack interconnect on the top surface of the base interposer includes coupling the base integrated circuit package to the top package carrier.
8. The method as claimed in claim 6 wherein the base interposer interconnect is used to couple the base package carrier and the base interposer.
9. A stacked integrated circuit package system comprising:
a base integrated circuit package including:
a base package carrier,
a base interposer mounted over the base package carrier, the base interposer having a central aperture,
a base intra-stack interconnect on a top surface of the base interposer,
a base interposer interconnect on a bottom surface of the base interposer; and
a flip chip mounted within the central aperture and on the base package carrier; and
a top integrated circuit package mounted on the base intra-stack interconnect and over the base interposer, the top integrated circuit package including:
a top interposer,
a top package carrier below the top interposer and with the base intra-stack interconnect on a bottom surface of the top package carrier and with the flip chip in direct contact with the bottom surface of the top package carrier, and
a top encapsulation on the top package carrier and the top interposer with a recess therein with the top interposer exposed by the recess.
10. The system as claimed in claim 9 wherein the flip chip is mounted over the base package carrier.
11. The system as claimed in claim 9 wherein the top integrated circuit package includes:
a first top integrated circuit device mounted on the top interposer; and
a second top integrated circuit device mounted on the top package carrier.
12. The system as claimed in claim 9 wherein the recess is over the top package carrier.
13. The system as claimed in claim 9 further comprising a base external interconnect formed below the base integrated circuit package.
14. The system as claimed in claim 9 further comprising a base underfill under the flip chip.
15. The system as claimed in claim 14 wherein the base intra-stack interconnect couples the base integrated circuit package to the top package carrier.
16. The system as claimed in claim 14 wherein the base interposer interconnect is used to couple the base package carrier and the base interposer.