IP Library › Granted Patent US 9,276,002
Granted Patent B2
US 9,276,002 · App. 14/734,310 · Granted Mar 1, 2016

Integrated circuit structure with bulk silicon FinFET

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Quick Facts
Patent No.
US 9,276,002
App. No.
14/734,310
Filed
Jun 9, 2015
Granted
Mar 1, 2016
Kind
B2
Art Unit
2898
USPC
257/347
Abstract

The present disclosure generally provides for an integrated circuit (IC) structure with a bulk silicon finFET and methods of forming the same. An IC structure according to the present disclosure can include: a bulk substrate; a finFET located on a first region of the bulk substrate; and a layered dummy structure located on a second region of the bulk substrate, wherein the layered dummy structure includes a first crystalline semiconductive layer, a second crystalline semiconductive layer positioned on the first crystalline semiconductive layer, wherein the first crystalline semiconductive layer comprises a material distinct from the second crystalline semiconductive layer, and a third crystalline semiconductive layer positioned on the second crystalline semiconductive layer, wherein the third crystalline semiconductive layer comprises the material distinct from the second crystalline semiconductive layer.

Claims (28)

1. An integrated circuit (IC) structure comprising:

a bulk substrate;

a finFET located on a first region of the bulk substrate; and

a layered dummy structure located on a second region of the bulk substrate, wherein the layered dummy structure includes:

a first crystalline semiconductive layer,

a second crystalline semiconductive layer positioned on the first crystalline semiconductive layer, wherein the first crystalline semiconductive layer comprises a material distinct from the second crystalline semiconductive layer, and

a third crystalline semiconductive layer positioned on the second crystalline semiconductive layer, wherein the third crystalline semiconductive layer comprises the material distinct from the second crystalline semiconductive layer.

2. The IC structure of claim 1 , further comprising an isolating film positioned between the layered dummy structure and the finFET.

3. The IC structure of claim 2 , wherein the isolating film comprises silicon oxide (SiO 2 ).

4. The IC structure of claim 1 , further comprising an insulator positioned between the bulk substrate and the finFET.

5. The IC structure of claim 4 , wherein a thickness of the insulator between the bulk substrate and the finFET is substantially equal to a thickness of the layered dummy structure.

6. The IC structure of claim 4 , wherein an interface between a semiconductor fin of the finFET and the insulator is substantially coplanar with an interface between the layered dummy structure and a semiconductor layer positioned thereon.

7. The IC structure of claim 1 , wherein the finFET comprises part of a dynamic random access memory (DRAM) component.

8. The IC structure of claim 1 , wherein the layered dummy structure has a thickness of at least approximately fifty nanometers.

9. The IC structure of claim 1 , wherein the first region of the bulk substrate is directly adjacent to the second region of the bulk substrate.

10. The IC structure of claim 1 , wherein the first and third crystalline semiconductive layers of the layered dummy structure comprise silicon germanium (SiGe), and the second crystalline semiconductive layer of the layered dummy structure comprises a material other than SiGe.

11. An integrated circuit (IC) structure comprising:

a bulk substrate;

a finFET located on a first region of the bulk substrate;

an insulating region positioned between the bulk substrate and the finFET; and

a layered dummy structure located on a second region of the bulk substrate, wherein the layered dummy structure includes:

a first crystalline semiconductive layer;

a second crystalline semiconductive layer positioned on the first crystalline semiconductive layer, wherein the first crystalline semiconductive layer comprises a material distinct from the second crystalline semiconductive layer; and

a third crystalline semiconductive layer positioned on the second crystalline semiconductive layer, wherein the third crystalline semiconductive layer comprises the material distinct from the second crystalline semiconductive layer, and wherein a thickness of the insulating region between the bulk substrate and the finFET is substantially equal to a thickness of the layered dummy structure.

12. The IC structure of claim 11 , wherein an interface between a semiconductor fin of the finFET and the insulating region is substantially coplanar with an interface between the layered dummy structure and a semiconductor layer positioned thereon.

13. The IC structure of claim 11 , wherein the finFET comprises part of a dynamic random access memory (DRAM) component.

14. The IC structure of claim 11 , wherein the first region of the bulk substrate is directly adjacent to the second region of the bulk substrate.

15. The IC structure of claim 11 , wherein the first and third crystalline semiconductive layers of the layered dummy structure comprise silicon germanium (SiGe), and the second crystalline semiconductive layer of the layered dummy structure comprises a material other than SiGe.