Method and apparatus of a fully-pipelined layered LDPC decoder
View Patent ↗The architecture is able to switch to Non-blocking check-node-update (CNU) scheduling architecture which has better performance than blocking CNU scheduling architecture. The architecture uses an Offset Min-Sum with Beta=1 with a clock domain operating at 440 MHz. The constraint macro-matrix is a spare matrix where each “1’ corresponds to a sub-array of a cyclically shifted identity matrix which is a shifted version of an identity matrix. Four core processors are used in the layered architecture where the constraint matrix uses a sub-array of 42 (check nodes)×42 (variable nodes) in the macro-array of 168×672 bits. Pipeline processing is used where the delay for each layer only requires 4 clock cycles.
1. An apparatus for communication systems comprising:
a first processor of a plurality of processors;
a last processor of said plurality of processors;
remaining processors of said plurality of processors coupled in series between said first processor and said last processor;
an output of said last processor coupled to an input of a de-multiplexor;
a plurality of memories each coupled to a corresponding output of said de-multiplexor; each input of a first multiplexor coupled to an output of a corresponding memory of said plurality of memories; and
an output of said first multiplexor coupled to a first input of said first processor.
2. The apparatus of claim 1 , further comprising:
a plurality of registers each storing a different portion of a plurality of data symbols;
each input of a second multiplexor coupled to an output of each corresponding said plurality of registers; and an output of said second multiplexor coupled to a second input of said first processor.
3. The apparatus of claim 2 , wherein said plurality of registers configured to behave as shift registers when storing incoming symbols.
4. The apparatus of claim 2 , wherein an iteration requires a number of clock cycles equal to a product of a count of said plurality of processors and a count of said plurality of registers.
5. The apparatus of claim 4 , wherein a fraction of said data symbols are randomly corrupted symbols.
6. The apparatus of claim 5 , wherein a log-likelihood ratio (LLR) is generated at said output of said last processor.
7. The apparatus of claim 6 , wherein said LLRs correct said randomly corrupted symbols.
8. The apparatus of claim 1 , wherein one of said plurality of memories is configured to be enabled.
9. The apparatus of claim 1 , wherein each of said plurality of processors perform a different function.
10. A method of reducing a wait state in a plurality of processors configured in a pipeline structure that operates on a plurality of layers of data, each layer comprising a plurality of groups of data, the method comprising:
coupling an output of a last processor in said pipeline structure to an input of a memory;
coupling an output of said memory to an input of a first processor in said pipeline structure;
for each group in each layer, applying a stored result read from said memory to said first processor in said pipeline; calculating a calculated result of said stored result at said output of said last processor; and storing said calculated result into said memory; and
operating at least one processor in said pipeline structure to process a next layer before a current layer is completed, wherein a stored result used by the next layer comprises a calculated result produced by a layer previous to the current layer.
11. The method of claim 10 , further comprising the steps of:
distributing equal portions of a plurality of data symbols among a corresponding plurality of registers;
coupling each input of a multiplexor to an output of each one of said corresponding plurality of registers; and
coupling an output of said multiplexor to a second input of said first processor in said pipeline structure.
12. The method of claim 11 , wherein an iteration requires a number of clock cycles equal to a product of a count of said plurality of processors and a count of said plurality of registers.
13. The method of claim 11 , wherein a fraction of said data symbols are randomly corrupted symbols.
14. The method of claim 13 , wherein a log-likelihood ratio (LLR) is generated at said output of said last processor.
15. The method of claim 14 , wherein said LLRs correct said randomly corrupted symbols.
16. The method of claim 10 , wherein said memory is configured to be enabled.
17. The method of claim 11 , wherein said plurality of registers configured to behave as shift registers when storing incoming symbols.
18. The method of claim 10 , wherein each of said plurality of processors perform a different function.
19. An apparatus for communication systems comprising:
a plurality of processors coupled in a pipeline structure;
an output of a last processor in said pipeline structure coupled to an input of a de-multiplexor;
a plurality of memories each coupled to a corresponding output of said de-multiplexor; each input of a first multiplexor coupled to an output of a corresponding memory of said plurality of memories;
an output of said first multiplexor coupled to a first input of a first processor in said pipeline structure;
a plurality of registers each storing a different portion of a plurality of data symbols; each input of a second multiplexor coupled to an output of each corresponding said plurality of registers; and
an output of said second multiplexor coupled to a second input of said first processor.
20. The apparatus of claim 19 , wherein each of said plurality of processors perform a different function, and a log-likelihood ratio (LLR) is generated at said output of said last processor.