Background auto-refresh apparatus and method for non-volatile memory array

1. A method for automatically refreshing a non-volatile memory array in the background without memory interruption, comprising:

a) selecting an unrefreshed segment of the non-volatile memory;

b) reading data from each row in the selected segment, and storing the data read from each row in a local temporary storage memory until an entire segment is read out;

c) remapping all memory addresses in the selected segment to the local temporary storage memory;

d) isolating column lines in the selected segment from global column lines of the non-volatile memory array;

e) erasing the data in the selected segment;

f) rewriting memory data in each row of the selected segment;

g) remapping all memory addresses in the selected segment to the non-volatile memory;

h) writing to a flag/index storage location the address of the last data successfully rewritten; and

repeating a) through h) until all segments have been refreshed.

2. The method of claim 1 , further including receiving a memory refresh signal before selecting an unrefreshed segment of the non-volatile memory.

3. The method of claim 1 wherein, reading data from each row in the selected segment, and storing the data read from each row in a local temporary storage memory until an entire segment is read out is performed during memory dead time.

4. The method of claim 1 wherein storing the data read from each row in a local temporary storage memory comprises storing the data read from each row in a local static read only memory (SRAM) block.

5. The method of claim 1 wherein storing the data read from each row in a local temporary storage memory comprises storing the data read from each row in a local non-volatile memory block.

6. Apparatus for automatically refreshing a non-volatile memory array in the background without memory interruption, comprising:

a set of output bit lines coupled to the memory array;

a dead-time detection circuit for detecting when no memory access requests are pending;

a temporary storage circuit coupled to the memory array and to the set of output bit lines for temporarily storing data from a selected group of rows in the memory array;

a circuit responsive to a memory refresh signal request including a selection circuit for selecting a selected group of rows in the memory array;

a circuit responsive to the dead-time circuit for reading data from the selected group of rows and writing the data into the temporary storage circuit the memory array;

a circuit for re-mapping addresses of the data from the selected group of rows during refresh to addresses in the temporary storage circuit containing the data and for re-mapping addresses of the data after refresh from the selected group of rows back to addresses in the memory array;

a circuit for writing to a flag/index storage location the address of the last data successfully rewritten; and

a circuit for erasing and re-programming the selected group of rows of the memory array.

7. The apparatus of claim 6 wherein the temporary storage circuit is a static read only memory (SRAM) block.

8. The apparatus of claim 6 wherein the temporary storage circuit is a non-volatile memory block.