IP Library Granted Patent US 9,350,376
Granted Patent B2
US 9,350,376 · App. 14/814,968 · Granted May 24, 2016

Frame adaptive digital to analog converter and methods for use therewith

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Quick Facts
Patent No.
US 9,350,376
App. No.
14/814,968
Filed
Jul 31, 2015
Granted
May 24, 2016
Kind
B2
Examiner
MAI, LAM T
Art Unit
2845
USPC
341/144
Abstract

A digital to analog converter (DAC) includes a thermometer coder that generates a plurality of micro-current source analog controls on a frame-by-frame or symbol-by-symbol basis and to process digital inputs from symbols or frames of data based on a thermometer coding to generate a plurality of micro-current source inputs. A plurality of micro-current sources generate a corresponding plurality of micro-current source outputs in response to the plurality of micro-current source inputs, wherein first selected ones of the plurality of micro-current sources are powered-off in response to the plurality of micro-current source analog controls for a first symbol or frame of the plurality of symbols or frames of data. A summing circuit generates an analog output based a sum of the corresponding plurality of micro-current source outputs.

Claims (38)

1. A digital to analog converter (DAC) comprising:

a first thermometer coder configured to process a digital input based on a first thermometer coding to generate a plurality of sub-DAC inputs and a plurality of sub-DAC analog controls;

a plurality of sub-DACs, coupled to the first thermometer coder, configured to generate a corresponding plurality of sub-DAC outputs in response to the plurality of sub-DAC inputs, wherein first selected ones of the plurality of sub-DACs are powered-off in response to the plurality of sub-DAC analog controls; and

a first summing circuit, coupled to the plurality of sub-DACs, configured to generate an analog output based a sum of the corresponding plurality of sub-DAC outputs.

2. The DAC of claim 1 wherein the first thermometer coder is configured to process a first portion of the digital input based on the first thermometer coding to generate the plurality of sub-DAC inputs and the plurality of sub-DAC analog controls.

3. The DAC of claim 2 wherein the first portion of the digital input includes a group of bits selected from the digital input.

4. The DAC of claim 2 wherein the first portion of the digital input includes a group of most significant bits selected from the digital input.

5. The DAC of claim 2 wherein at least one of the plurality of sub-DACs includes:

a second thermometer coder configured to process a second portion of the digital input based on a second thermometer coding to generate a plurality of micro-current source inputs and a plurality of micro-current source analog controls;

a plurality of micro-current sources, coupled to the second thermometer coder, configured to generate a corresponding plurality of micro-current source outputs in response to the plurality of micro-current source inputs, wherein first selected ones of the plurality of micro-current sources are powered-off in response to the plurality of micro-current source analog controls; and

a second summing circuit, coupled to the plurality of micro-current sources, configured to generate a corresponding one of the plurality of sub-DAC outputs based a sum of the corresponding plurality of micro-current source outputs.

6. The DAC of claim 5 wherein the plurality of micro-current source outputs have one of: a positive current state, a negative current state and a neutral current state.

7. The DAC of claim 1 wherein the first thermometer coder is configured to process a first value of the digital input based on the first thermometer coding to generate the plurality of sub-DAC inputs to ramp from a prior value of the analog output to a new value corresponding the first value of the digital input.

8. A digital to analog converter (DAC) comprising:

a sub-DAC coder configured to process a digital input to generate a plurality of sub-DAC inputs and a plurality of sub-DAC analog controls;

a plurality of sub-DACs, coupled to the sub-DAC coder, configured to generate a corresponding plurality of sub-DAC outputs in response to the plurality of sub-DAC inputs, wherein first selected ones of the plurality of sub-DACs are powered-off in response to the plurality of sub-DAC analog controls; wherein at least one of the plurality of sub-DACs includes:

a thermometer coder configured to process a second portion of the digital input based on a thermometer coding to generate a plurality of micro-current source inputs and a plurality of micro-current source analog controls;

a plurality of micro-current sources, coupled to the thermometer coder, configured to generate a corresponding plurality of micro-current source outputs in response to the plurality of micro-current source inputs, wherein first selected ones of the plurality of micro-current sources are powered-off in response to the plurality of micro-current source analog controls; and

a first summing circuit, coupled to the plurality of micro-current sources, configured to generate a corresponding one of the plurality of sub-DAC outputs based a sum of the corresponding plurality of micro-current source outputs; and

a second summing circuit, coupled to the plurality of sub-DACs, configured to generate an analog output based a sum of the corresponding plurality of sub-DAC outputs.

9. The DAC of claim 8 wherein the sub-DAC coder is configured to process a first portion of the digital input to generate the plurality of sub-DAC inputs and the plurality of sub-DAC analog controls.

10. The DAC of claim 9 wherein the first portion of the digital input includes a group of bits selected from the digital input.

11. The DAC of claim 9 wherein the first portion of the digital input includes a group of most significant bits selected from the digital input.

12. The DAC of claim 8 wherein the plurality of micro-current source outputs have one of: a positive current state, a negative current state and a neutral current state.

13. The DAC of claim 8 wherein the sub-DAC coder is configured to process a first value of the digital input to generate the plurality of sub-DAC inputs to ramp from a prior value of the analog output to a new value corresponding the first value of the digital input.

14. A method for us in a digital to analog converter (DAC), the method comprising:

processing a digital input based on a thermometer coding to generate a plurality of sub-DAC inputs and a plurality of sub-DAC analog controls;

generating, via a plurality of sub-DACs, a corresponding plurality of sub-DAC outputs in response to the plurality of sub-DAC inputs;

powering off first selected ones of the plurality of sub-DACs in response to the plurality of sub-DAC analog controls; and

generating an analog output based a sum of the corresponding plurality of sub-DAC outputs.

15. The method of claim 14 wherein the thermometer coding processes a first portion of the digital input to generate the plurality of sub-DAC inputs and the plurality of sub-DAC analog controls.

16. The method of claim 15 wherein the first portion of the digital input includes a group of bits selected from the digital input.

17. The method of claim 15 wherein the first portion of the digital input includes a group of most significant bits selected from the digital input.

18. The method of claim 14 further comprising:

processing a first value of the digital input based on the thermometer coding to generate the plurality of sub-DAC inputs to ramp from a prior value of the analog output to a new value corresponding the first value of the digital input.

19. The method of claim 14 , wherein the plurality of sub-DAC analog controls are generated on a frame-by-frame basis.

20. The method of claim 19 wherein powering off first selected ones of the plurality of sub-DACs in response to the plurality of sub-DAC analog controls includes powering off first selected ones of the plurality of sub-DACs in response to the plurality of sub-DAC analog controls for a first frame of the digital input, and the method further comprises:

powering-off second selected ones of the plurality of sub-DACs in response to the plurality of sub-DAC analog controls for a second frame of the digital input.