Spread-spectrum clock generator
View Patent ↗A spread-spectrum clock (SSC) generator for generating an SSC signal. The SSC generator has a first up/down counter that operates for a fixed, first duration (t1), a first PRBS generator that operate for a variable, second duration (t2), a second up/down counter that operates for a fixed, third duration (t3), and a second PRBS generator that operates for a variable, fourth duration (t4). A state machine sequentially triggers the first counter and the first PRBS generator to generate a positive portion of a cycle of the SSC signal and then sequentially triggers the second counter and the second PRBS generator to generate a negative portion of the cycle of the SSC signal. For a set of parameters stored in configurable registers, the first and third durations are fixed from cycle to cycle, while the second and fourth durations vary from cycle to cycle.
1. A spread-spectrum clock (SSC) generator for generating an SSC signal, the SSC generator comprising:
a first counter that operates for a first duration (t1) corresponding to a fixed part of a positive portion of an SSC cycle of the SSC signal;
a first random generator that operates for a second duration (t2) corresponding to a variable part of the positive portion of the SSC cycle;
a second counter that operates for a third duration (t3) corresponding to a fixed part of a negative portion of the SSC cycle;
a second random generator that operates for a fourth duration (t4) corresponding to a variable part of the negative portion of the SSC cycle;
a set of configurable registers that store parameters to control operations of the first and second counters and the first and second random generators; and
a state machine that sequentially triggers the first and second counters and the first and second random generators in a specified order to generate the SSC cycle,
wherein each counter is an up-down counter.
2. The SSC generator of claim 1 , wherein the specified order is t1, then t2, then t3, then t4.
3. The SSC generator of claim 1 , wherein each random generator is a pseudo-random binary sequence (PRBS) generator.
4. The SSC generator of claim 1 , wherein, for a set of parameters stored in the registers:
the first duration is fixed from cycle to cycle of the SSC signal;
the third duration is fixed from cycle to cycle of the SSC signal; and
the second and fourth durations vary from cycle to cycle of the SSC signal.
5. The SSC generator of claim 1 , wherein each counter and each random generator are configurable to be independently selected or disabled.
6. The SSC generator of claim 1 , wherein:
each random generator is a PRBS generator;
for a set of parameters stored in the registers:
the first duration is fixed from cycle to cycle of the SSC signal;
the third duration is fixed from cycle to cycle of the SSC signal; and
the second and fourth durations vary from cycle to cycle of the SSC signal; and
each counter and each random generator are configurable to be independently selected or disabled.
7. The SSC generator of claim 6 , wherein the specified order is t8, then t2, then t3, then t4.
8. A spread-spectrum clock (SSC) generator for generating an SSC signal, the SSC generator comprising:
a first counter that operates for a first duration (t1) corresponding to a fixed part of a positive portion of an SSC cycle of the SSC signal;
a first random generator that operates for a second duration (t2) corresponding to a variable part of the positive portion of the SSC cycle;
a second counter that operates for a third duration (t3) corresponding to a fixed part of a negative portion of the SSC cycle;
a second random generator that operates for a fourth duration (t4) corresponding to a variable part of the negative portion of the SSC cycle;
a set of configurable registers that store parameters to control operations of the first and second counters and the first and second random generators; and
a state machine that sequentially triggers the first and second counters and the first and second random generators in a specified order to generate the SSC cycle,
wherein, for a set of parameters stored in the registers:
the first duration is fixed from cycle to cycle of the SSC signal;
the third duration is fixed from cycle to cycle of the SSC signal; and
the second and fourth durations vary from cycle to cycle of the SSC signal.
9. A spread-spectrum clock (SSC) generator for generating an SSC signal, the SSC generator comprising:
a first counter that operates for a first duration (t1) corresponding to a fixed part of a positive portion of an SSC cycle of the SSC signal;
a first random generator that operates for a second duration (t2) corresponding to a variable part of the positive portion of the SSC cycle;
a second counter that operates for a third duration (t3) corresponding to a fixed part of a negative portion of the SSC cycle;
a second random generator that operates for a fourth duration (t4) corresponding to a variable part of the negative portion of the SSC cycle;
a set of configurable registers that store parameters to control operations of the first and second counters and the first and second random generators; and
a state machine that sequentially triggers the first and second counters and the first and second random generators in a specified order to generate the SSC cycle,
wherein each counter and each random generator are configurable to be independently selected or disabled.