Semiconductor storage device and test method thereof using a common bit line
View Patent ↗Provided is a semiconductor storage device including: first memory cells; first word lines; first bit lines; a first common bit line; second memory cells; second word lines; second bit lines; a second common bit line; a first selection circuit that connects the first common bit line to a first bit line selected from the first bit lines; a second selection circuit that connects the second common bit line to a second bit line selected from the second bit lines; a word line driver that activates any one of the first and second word lines; a reference current supply unit that supplies a reference current to a common bit line among the first and second common bit lines, the common bit line not being electrically connected to a data read target memory cell; and a sense amplifier that amplifies a potential difference between the first and second common bit lines.
1. A semiconductor storage device comprising:
a plurality of memory cells provided in a matrix manner;
a plurality of write word lines and a plurality of read word lines, the write word lines and the read word lines being respectively provided in a plurality of rows of the plurality of memory cells;
a plurality of write bit line pairs and a plurality of read bit lines, the write bit line pairs and the read bit lines being respectively provided in a plurality of columns of the plurality of memory cells;
a write word line driver that activates any of the plurality of write word lines;
a read word line driver that activates any of the plurality of read word lines;
a write selection circuit that selects any of the plurality of write bit line pairs;
a read selection circuit that selects any of the plurality of read bit lines;
an input driver that outputs write data to a write bit line pair selected by the write selection circuit;
a sense amplifier that amplifies a potential difference between a reference potential and a potential of a read bit line selected by the read selection circuit; and
a test control circuit that activates, during a test mode, any of the write word lines, and further activates, after a lapse of a predetermined period of time, the read word line in the same row as the any of the write word lines.
2. The semiconductor storage device according to claim 1 , wherein the test control circuit makes the read word lines inactive, and thereafter makes the any of the write word lines inactive.
3. A test method of a semiconductor storage device, the semiconductor storage device comprising:
a plurality of memory cells provided in a matrix manner;
a plurality of write word lines and a plurality of read word lines, the write word lines and the read word lines being respectively provided in a plurality of rows of the plurality of memory cells;
a plurality of write bit line pairs and a plurality of read bit lines, the write bit line pairs and the read bit lines being respectively provided in a plurality of columns of the plurality of memory cells;
a write word line driver that activates any of the plurality of write word lines;
a read word line driver that activates any of the plurality of read word lines;
a write selection circuit that selects any of the plurality of write bit line pairs;
a read selection circuit that selects any of the plurality of read bit lines;
an input driver that outputs write data to a write bit line pair selected by the write selection circuit; and
a sense amplifier that amplifies a potential difference between a reference potential and a potential of a read bit line selected by the read selection circuit,
the method comprising:
activating, during a test mode, any of the write word lines, and further activating, after a lapse of a predetermined period of time, the read word line in the same row as the any of the write word lines.
4. The test method of a semiconductor storage device according to claim 3 , further comprising making the read word lines inactive, and thereafter making the any of the write word lines inactive.