Sense amplifier and latching scheme

1. A circuit, comprising:

a sense amplifier circuit which comprises a plurality of transistors enabled by a sense amplifier enable signal to output a first output data line true signal and a second output data line complement signal to a latching circuit; and

the latching circuit which comprises a primary driver actively driven by the first output data line true signal and a secondary driver actively driven by the second output data line complement signal such that the latching circuit outputs a read global data line,

wherein the secondary driver comprises a NMOS pull-up device and a PMOS pull-down device, and another transistor is directly connected between a source of the NMOS pull-up device and a source of the PMOS pull-down device, and

a source of the another transistor is directly connected to the source of the NMOS pull-up device, a drain of the another transistor is directly connected to the source of the PMOS pull-down device, and a gate of the another transistor is directly connected to an inverted signal of the sense amplifier enable signal.

2. The circuit of claim 1 , wherein the primary driver comprises a PMOS pull-up device and a NMOS pull-down device.

3. The circuit of claim 2 , wherein a gate of the PMOS pull-up device and a gate of the NMOS pull-down device are both connected to the first output data line true signal.

4. The circuit of claim 1 , wherein a gate of the NMOS pull-up device and a gate of the PMOS pull-down device are both connected to the second output data line complement signal.

5. The circuit of claim 1 , wherein a load on the first output data line true signal is equivalent to a load on the second output data line complement signal.

6. The circuit of claim 1 , wherein the primary driver and the secondary driver have a common voltage supply.

7. The circuit of claim 1 , wherein the plurality of transistors in the sense amplifier circuit comprises five PMOS transistors and three NMOS transistors.

8. The circuit of claim 1 , wherein the sense amplifier circuit and the latching circuit comprise a static random access memory (SRAM) device.

9. The circuit of claim 1 , wherein the sense amplifier circuit and the latching circuit comprise one of a dynamic random access memory (DRAM) device, another volatile memory device, and a non-volatile memory device.

10. A circuit, comprising:

a sense amplifier circuit which comprises a plurality of transistors enabled by a sense amplifier enable signal to output a first output data line true signal and a second output data line complement signal to a latching circuit;

the latching circuit which comprises a PMOS pull-up device and a NMOS pull-down device which are actively driven by the first output data line true signal and a NMOS pull-up device and a PMOS pull-down device which are actively driven by the second output data line complement signal such that the latching circuit outputs a read global data line; and

another transistor which is directly connected between a source of the NMOS pull-up device and a source of the PMOS pull-down device,

wherein a source of the another transistor is directly connected to the source of the NMOS pull-up device, a drain of the another transistor is directly connected to the source of the PMOS pull-down device, and a gate of the another transistor is directly connected to an inverted signal of the sense amplifier enable signal.

11. The circuit of claim 10 , wherein a gate of the PMOS pull-up device and a gate of the NMOS pull-down device are both connected to the first output data line true signal.

12. The circuit of claim 10 , wherein a gate of the NMOS pull-up device and a gate of the PMOS pull-down device are both connected to the second output data line complement signal.

13. The circuit of claim 10 , wherein a load on the first output data line true signal is equivalent to a load on the second output data line complement signal.

14. The circuit of claim 10 , wherein the primary driver and the secondary driver have a common voltage supply.

15. The circuit of claim 10 , wherein the plurality of transistors in the sense amplifier circuit comprises five PMOS transistors and three NMOS transistors.

16. A method, comprising:

enabling a sense amplifier circuit to output a first output data line true signal and a second output data line complement signal to a latching circuit;

actively driving a primary driver of the latching circuit by the first output data line true signal;

actively driving a secondary driver of the latching circuit by the second output data line complement signal; and

outputting a read global data line based on the primary driver and the secondary driver being actively driven through another transistor which is connected between a source of a NMOS pull-up device of the secondary driver and a source of a PMOS pull-down device of the secondary driver,

wherein a source of the another transistor is directly connected to the source of the NMOS pull-up device, a drain of the another transistor is directly connected to the source of the PMOS pull-down device, and a gate of the another transistor is directly connected to an inverted signal of a sense amplifier enable signal.

17. The method of claim 16 , wherein a load on the first output data line true signal is equivalent to a load on the second output data line complement signal.

18. The method of claim 16 , wherein the primary driver and the secondary driver have a common voltage supply.

19. The method of claim 16 , wherein the primary driver comprises a PMOS pull-up device and a NMOS pull-down device.