Latching current sensing amplifier for memory array

1. A current sense-amplifier circuit comprising:

a first pair of series connected transistors; and

a second pair of series connected transistors,

wherein the first pair of series connected transistors and the second pair of series connected transistors are configured with a common gate node and

wherein the first pair of series connected transistors and the second pair of series connected transistors are configured for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.

2. The current sense-amplifier circuit of claim 1 , wherein the first pair of series connected transistors and the second pair of series connected transistors are wired as a self-biased circuit.

3. The current sense-amplifier circuit of claim 1 , wherein the first pair of series connected transistors and the second pair of series connected transistors each further comprises, an output-drain node, an intermediate node, and an input-source node.

4. The current sense-amplifier circuit of claim 3 , wherein the output-drain node for the first pair of series connected transistors and the output-drain node for the second pair of series connected transistors are connected to a pair of first current sources.

5. The current sense-amplifier circuit of claim 3 , wherein the intermediate node for the first pair of series connected transistors and the intermediate node for the second pair of series connected transistors are connected to a pair of sense lines.

6. The current sense-amplifier circuit of claim 3 , wherein the input-source node for the first pair of series connected transistors and the input-source node for the second pair of series connected transistors are connected to a power supply.

7. The current sense-amplifier circuit of claim 3 , wherein in the sense operation, the common gate node for the first pair of series connected transistors and the second pair of series connected transistors is coupled together to the output-drain node, and

wherein in the latching operation, the common gate node is separated and the first pair of series connected transistors and the second pair of series connected transistors are reconfigured in a cross-coupled arrangement.

8. The current sense-amplifier circuit of claim 7 , wherein the common gate node, in response to being enabled by a sense signal, selectively shorts gates of the first pair of series connected transistors to gates of the second pair of series connected transistors.

9. The current sense-amplifier circuit of claim 7 , wherein a first transistor of each of the first pair of series connected transistors and the second pair of series connected transistors injects a first current into a bitline true (BLT) and a bitline complement (BLC).

10. The current sense-amplifier circuit of claim 9 , wherein a second current is drawn out of the BLT and BLC from a differential memory cell by a pair of stacked transistors.

11. The current sense-amplifier circuit of claim 10 , wherein each of the first pair of series connected transistors and the second pair of series connected transistors is connected to a common node to form self biased current sources.

12. The current sense-amplifier circuit of claim 3 , wherein the first pair of series connected transistors and the second pair of series connected transistors are p-type transistors (PFETs).

13. The current sense-amplifier circuit of claim 12 , wherein a true bitline (BLT) of a differential memory cell is coupled at the intermediate node of the first pair of series connected transistors and a complementary bitline (BLC) of a differential memory cell is coupled at the intermediate node of the second pair of series connected transistors.

14. The current sense-amplifier circuit of claim 13 , wherein the first pair of series connected transistors and the second pair of series connected transistors are each coupled in series to stacked transistors which pull a differential current from the differential memory cell through the BLT and BLC to OUT_ANALOG.

15. The current sense-amplifier circuit of claim 12 , further comprising an isolation device to isolate the first pair of series connected transistors and the second pair of series connected transistors from a differential memory cell.