Nanowire-based vertical memory cell array having a back plate and nanowire seeds contacting a bit line
View Patent ↗The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator. At least one bitline extending on a top of the plurality of vertical nanowires and in electrical contact therewith; and at least one wordline formed on vertical sidewalls of the plurality of vertical nanowires and separated therefrom by the dielectric material.
1. A vertical memory cell array, comprising:
a plurality of vertical nanowires extending from an insulator layer;
a dielectric material on vertical sidewalls of the plurality of vertical nanowires;
doped material provided between the plurality of vertical nanowire;
at least one bitline extending on a top of the plurality of vertical nanowires and in electrical contact therewith;
nanowire seeds on a top of each of the plurality of nanowires and in electrical contact with the at least one bit line; and
at least one wordline formed on the vertical sidewalls of the plurality of vertical nanowires and separated therefrom by the dielectric material.
2. The vertical memory cell array of claim 1 , wherein the dielectric material is a high-k dielectric material.
3. The vertical memory cell array of claim 1 , wherein the doped material is polysilicon.
4. The vertical memory cell array of claim 3 , wherein the doped polysilicon is one of N+ doped material and P+ doped material.
5. The vertical memory cell array of claim 3 , wherein the doped polysilicon is below the at least one wordline and acts as a common back plate and the at least one wordline is separated from the common back plate by an insulator material.
6. The vertical memory cell array of claim 1 , wherein the plurality of vertical nanowires are composed of semiconductor material.
7. The vertical memory cell array of claim 1 , wherein the nanowire seeds are electrically isolated from the at least one wordline by a recessing of the at least one wordline below the nanowire seeds.
8. A vertical memory cell, comprising:
a plurality of vertical nanowires;
a high-k dielectric material on vertical sidewalls of the plurality of vertical nanowires;
doped polysilicon material provided between the plurality of vertical nanowires;
at least one metal formed on vertical sidewalls of the plurality of vertical nanowires over the high-k dielectric material and electrically isolated from the doped polysilicon material;
at least one metal extending on a top of the plurality of vertical nanowires, in electrical contact with the plurality of vertical nanowires and electrically isolated from the doped polysilicon material; and
nanowire seeds on a top of each of the plurality of nanowires and in electrical contact with the at least one metal extending on the top of the plurality of vertical nanowires, wherein the nanowire seeds are electrically isolated from the at least one metal formed on vertical sidewalls of the plurality of vertical nanowires.
9. The vertical memory cell of claim 8 , wherein the high-k dielectric material is a hafnium based material.
10. The vertical memory cell of claim 8 , wherein the doped polysilicon is one of N+ doped material and P+ doped material, which is below the at least one metal formed on the vertical sidewalls and acts as a common back plate.