Automatic resolution detection

1. A method for automatic mode detection and scaler control for a display device digitally coupled to a display controller, the display controller having a variable active horizontal resolution and a variable active vertical resolution, the display device having a fixed horizontal resolution and a fixed vertical resolution, comprising:

determining the variable active horizontal resolution of the display controller by counting a pixel clock;

determining the variable active vertical resolution of the display controller by counting active horizontal lines between vertical sync pulses; and

scaling the output of the display controller, correlative to the determined variable active horizontal resolution and the determined variable active vertical resolution, to match the fixed horizontal resolution and the fixed vertical resolution of the display device.

2. The method of claim 1 , wherein counting of the pixel clock is driven by a valid pixel signal.

3. The method of claim 2 , wherein the valid pixel signal is DATA_ENABLE.

4. The method of claim 1 , wherein the variable active horizontal lines are determined by counting a horizontal sync pulse qualified with DATA_ENABLE between vertical sync pulses.

5. The method of claim 1 , wherein the variable active horizontal lines are determined by counting DATA_ENABLE between vertical sync pulses.

6. The method of claim 1 , further comprising assigning display device horizontal and vertical resolutions from a panel size decoder.

7. The method of claim 1 , wherein scaling the output of the display controller to the fixed horizontal resolution of the display device comprises dividing the fixed horizontal resolution of the display device by the determined variable active horizontal resolution.

8. The method of claim 1 , wherein scaling the output of the display controller to the fixed vertical resolution of the display device comprises dividing the fixed vertical resolution of the display device by the determined variable active vertical resolution.

9. An apparatus to perform mode detection and scaler control in a system with a display controller and a display device, the display device having a scaler circuit for receiving incoming signal resolution and scaling outgoing signal to a display device horizontal resolution and a display device vertical resolution, comprising:

a horizontal counter coupled to the display controller output, the horizontal counter determining an active horizontal resolution by counting a pixel clock;

a vertical counter coupled to the display controller output, the vertical counter determining an active vertical resolution by counting active horizontal lines between vertical sync pulses;

a panel size decoder for receiving panel size selection from a user, the panel size decoder configured to provide output signals based on the panel size selection, the output signals representative of the display device horizontal resolution and the display device vertical resolution; and

a control circuit coupled to the horizontal counter, the vertical counter, and the panel size decoder, the control circuit scaling the output of the display controller by a horizontal scale factor and a vertical scale factor to match the horizontal resolution and the vertical resolution, respectively, of the display device if the active horizontal resolution and the active vertical resolution differ from the respective display device horizontal and vertical resolutions.

10. The apparatus of claim 9 , wherein counting of the pixel clock is driven by a valid pixel signal.

11. The apparatus of claim 10 , wherein the valid pixel signal is DATA_ENABLE.

12. The apparatus of claim 9 , wherein the variable active horizontal lines are determined by counting a horizontal sync pulse qualified with DATA_ENABLE between vertical sync pulses.

13. The apparatus of claim 9 , wherein the variable active horizontal lines are determined by counting DATA_ENABLE between vertical sync pulses.

14. The apparatus of claim 9 , wherein the horizontal scale factor is determined by dividing the display device horizontal resolution by the determined horizontal resolution.

15. The apparatus of claim 9 , wherein the vertical scale factor is determined by dividing the display device vertical resolution by the determined vertical resolution.

16. A computer system, comprising:

a processor;

a data storage device coupled to the processor;

a display controller coupled processor;

a display device coupled to the processor, the display device having a scaler circuit for receiving incoming signal resolution and scaling outgoing signal to a display device horizontal resolution and a display device vertical resolution; and

an apparatus to perform mode detection and scaler control coupled to the processor, comprising:

a horizontal counter coupled to the display controller output, the horizontal counter determining an active horizontal resolution by counting a pixel clock;

a vertical counter coupled to the display controller output, the vertical counter determining an active vertical resolution by counting active horizontal lines between vertical sync pulses;

a panel size decoder for receiving panel size selection from a user, the panel size decoder configured to provide output signals based on the panel size selection, the output signals representative of the display device horizontal resolution and the display device vertical resolution; and

a control circuit coupled to the horizontal counter, the vertical counter, and the panel size decoder, the control circuit scaling the output of the display controller by a horizontal scale factor and a vertical scale factor to match the horizontal resolution and vertical resolution, respectively, of the display device if the active horizontal resolution and the active vertical resolution differ from the respective display device horizontal and vertical resolutions.

17. The system of claim 16 , wherein counting of the pixel clock is driven by a valid pixel signal.

18. The system of claim 17 , wherein the valid pixel signal is DATA_ENABLE.

19. The system of claim 16 , wherein the variable active horizontal lines are determined by counting a horizontal sync pulse qualified with DATA_ENABLE between vertical sync pulses.

20. The system of claim 16 , wherein the variable active horizontal lines are determined by counting DATA_ENABLE between vertical sync pulses.

21. The system of claim 16 , wherein the horizontal scale factor is determined by dividing the display device horizontal resolution by the determined horizontal resolution.

22. The system of claim 16 , wherein the vertical scale factor is determined by dividing the display device vertical resolution by the determined vertical resolution.

23. A method for automatic mode detection and scaler control for a display device digitally coupled to a display controller, the display controller having a variable active horizontal resolution and a variable active vertical resolution, the display device having a fixed horizontal resolution and a fixed vertical resolution, the method comprising the acts of:

counting valid pixels between horizontal sync pulses;

determining the variable active horizontal resolution of the display controller based on the act of counting valid pixels;

counting active horizontal lines between vertical sync pulses;

determining the variable active vertical resolution of the display controller based on the act of counting active horizontal lines; and

scaling the output of the display controller, correlative to the determined variable active horizontal resolution and the determined variable active vertical resolution, to match the fixed horizontal resolution and the fixed vertical resolution of the display device.

24. The method as recited in claim 23 , wherein the act of counting valid pixels between horizontal sync pulses comprises the act counting a pixel clock.

25. The method as recited in claim 24 , wherein the act of counting a pixel clock is driven by a valid pixel signal.

26. The method as recited in claim 25 , wherein the valid pixel signal is DATA — ENABLE.

27. The method as recited in claim 23 , wherein the act of counting active horizontal lines between vertical sync pulses comprises the act of counting a horizontal sync pulse qualified with DATA_ENABLE between vertical sync pulses.

28. The method as recited in claim 23 , wherein the act of counting active horizontal lines between vertical sync pulses comprises the act of counting DATA_ENABLE between vertical sync pulses.

29. An apparatus to perform mode detection and scaler control in a system with a display controller and a display device, the display device having a scaler circuit for receiving incoming signal resolution and scaling outgoing signal to a display device horizontal resolution and a display device vertical resolution, the apparatus comprising:

a horizontal counter coupled to the display controller output to determine an active horizontal resolution by counting valid pixels between horizontal sync pulses;

a vertical counter coupled to the display controller output to determine an active vertical resolution;

a panel size circuit configured to provide output signals representative of the display device horizontal resolution and the display device vertical resolution; and

a control circuit coupled to the horizontal counter, the vertical counter, and the panel size circuit, the control circuit configured to scale the output of the display controller by a horizontal scale factor and a vertical scale factor to match the display device horizontal resolution and the display device vertical resolution, respectively, if either the active horizontal resolution or the active vertical resolution differs from the respective display device horizontal and vertical resolutions.

30. The apparatus as recited in claim 29 , wherein the counting of valid pixels comprises counting a pixel clock.

31. The apparatus as recited in claim 30 , wherein the counting of the pixel clock is driven by a valid pixel signal.

32. The apparatus as recited in claim 31 , wherein the valid pixel signal is DATA_ENABLE.

33. The apparatus as recited in claim 29 , wherein the vertical counter is configured to determine the active vertical resolution by counting active horizontal lines between vertical sync pulses.