Feedforward clock switching circuit
View Patent ↗A clocking circuit includes primary and secondary clock sources. These sources are input to a multiplexer which selectively chooses between them. A PLL stabilizes the output of the multiplexer. A clock detection circuit monitors the presence of the primary clock source and drives the multiplexer such that if the primary clock source fails, the backup clock is selected. Also upon clock switchover, a feedforward correction circuitry modifies a time constant within the PLL to mitigate clock skew during switchover.
1. A clock circuit comprising:
first and second clock sources;
a multiplexer having a first input coupled to the first clock source, a second input coupled to the second clock source, and an output selectively couplable to said first and second inputs;
a clock detection circuit having an output representing a presence of said first clock source;
said multiplexer having a selection input coupled to said clock detection circuit output such that said multiplexer selects said first clock source as its output when said first clock source is present;
a phase-locked loop circuit (“PLL”) having
an input coupled to said multiplexer output; and
a frequency output;
said PLL including a feedback filter circuit; and
feedforward circuitry coupled to said feedback filter circuit and to said clock detection circuit output, said feedforward circuitry selectively coupling at least one circuit element to said feedback filter circuit, wherein said feedforward circuitry selective coupling is controlled by said clock detection circuit output.
2. The circuit of claim 1 , where said feedforward circuitry includes a switch controlled by said clock detection circuit output and performing said selective coupling.
3. The circuit of claim 2 , wherein said switch comprises a transistor.
4. The circuit of claim 2 , wherein said at least one circuit element includes a resistor.
5. The circuit of claim 4 , wherein said at least one circuit element includes a capacitor in parallel with said resistor.
6. The circuit of claim 2 , wherein said feedforward circuitry includes at least one of a resistor and a capacitor in parallel with said switch.
7. The circuit of claim 2 , further including a bias circuit coupling said clock detection circuit output to said switch.
8. The circuit of claim 7 , wherein said bias network includes a resistor based voltage divider.
9. The circuit of claim 8 , further including a zener diode in parallel with at least one resistor of said resistor base voltage divider.
10. The circuit of claim 1 , wherein said first clock source is received from another clock circuit within a common system.
11. The circuit of claim 10 , wherein said first clock source is received over a bus.
12. The circuit of claim 11 , wherein said second clock source comprises a local oscillator.
13. The circuit of claim 12 , wherein said second clock source is provided to said bus.
14. A system comprising:
multiple clock sources;
a switch having multiple inputs, said multiple inputs being respectively coupled to said multiple clock sources;
a clock detection circuit having an output representing a presence of one of said multiple clock sources;
said switch having a selection input coupled to said clock detection circuit output such that said switch selects one particular clock source of said multiple clock sources as its output when said one particular clock source is present;
a phase-locked loop circuit (“PLL”) having
an input coupled to said switch output; and
a frequency output;
said PLL including a feedback filter circuit; and
feedforward circuitry coupled to said feedback filter circuit and to said clock detection circuit output, said feedforward circuitry selectively coupling at least one circuit element to said feedback filter circuit, wherein said feedforward circuitry selective coupling is controlled by said clock detection circuit output.