Method of regulating a target system using a frequency comparison of feedback and reference pulse trains

1. A method of regulating a target system, comprising the steps of:

providing a reference signal;

generating a plurality of digital signals defining a reference pulse train with a frequency dependent upon said reference signal;

providing a target system to be regulated, said target system having an output in the form of a plurality of digital signals defining a feedback pulse train having a frequency;

comparing said frequency of said reference pulse train with said frequency of said feedback pulse train and substantially aligning a leading edge of each digital signal in said reference pulse train with a leading edge of each digital signal in said feedback pulse train;

generating a control signal dependent upon said comparison without regard to phase locking said feedback pulse train to said reference signal; and

providing said control signal as an input to said target system.

2. The method of regulating a target system of claim 1 , wherein said step of generating said control signal comprises the substep of generating a proportional error pulse train including a plurality of digital signals, each said digital signal representing an error between a corresponding pair of aligned digital signals of said reference pulse train and said feedback pulse train.

3. The method of regulating a target system of claim 2 , wherein said step of generating said control signal comprises the further substep of generating an error direction pulse train including a plurality of digital signals, each said digital signal representing a directionality of said error between said corresponding pair of aligned digital signals.

4. A method of regulating a target system, comprising the steps of:

providing a reference signal;

generating a plurality of digital signals defining a reference pulse train with a frequency dependent upon said reference signal;

providing a target system to be regulated, said target system having an output in the form of a plurality of digital signals defining a feedback pulse train having a frequency;

comparing said frequency of said reference pulse train with said frequency of said feedback pulse train;

substantially aligning a leading edge of each digital signal in said reference pulse train with a leading edge of each digital signal in said feedback pulse train;

generating a control signal dependent upon said comparison without regard to phase locking said feedback pulse train to said reference signal, said generating step including the substeps of:

generating a proportional error pulse train including a plurality of digital signals, each said digital signal representing an error between a corresponding pair of aligned digital signals of said reference pulse train and said feedback pulse train;

counting up from zero with a first proportional clock CP 1 at a frequency fP 1 when said digital signals of said proportional error pulse train are in a high state;

resetting said first proportional clock CP 1 to zero when said digital signals of said proportional error pulse train are in a low state;

loading a current value of said first proportional clock CP 1 into a second proportional clock CP 2 each time said first proportional clock CP 1 transitions from a high state to a low state;

counting down from said loaded current value with said second proportional clock CP 2 at a frequency fP 2 until a zero value is reached; and

determining a proportional error term representing a time average of a signal which is held high while said second proportional clock CP 2 is in a high state and held low while said second proportional clock CP 2 is in a zero state, said control signal being dependent upon said proportional error term; and

providing said control signal as an input to said target system.

5. A method of regulating a target system, comprising the steps of:

providing a reference signal;

generating a plurality of digital signals defining a reference pulse train with a frequency dependent upon said reference signal;

providing a target system to be regulated, said target system having an output in the form of a plurality of digital signals defining a feedback pulse train having a frequency;

comparing said frequency of said reference pulse train with said frequency of said feedback pulse train, and substantially aligning a leading edge of each digital signal in said reference pulse train with a leading edge of each digital signal in said feedback pulse train;

generating a control signal dependent upon said comparison without regard to phase locking said feedback pulse train to said reference signal, said generating step including the substeps of:

generating a proportional error pulse train including a plurality of digital signals, each said digital signal representing an error between a corresponding pair of aligned digital signals of said reference pulse train and said feedback pulse train;

generating an error direction pulse train including a plurality of digital signals, each said digital signal representing a directionality of said error between said corresponding pair of aligned digital signals;

counting up from zero with a first integral clock CI 1 at a frequency fI 1 when said digital signals of said proportional error pulse train are in a high state and said digital signals of said error direction pulse train are simultaneously in a high state;

counting down with said first integral clock Cl 1 at said frequency fl 1 when said digital signals of said proportional error pulse train are in a high state and said digital signals of said error direction pulse train are in a low state;

maintaining said first integral clock CI 1 at a current value when said digital signals of said proportional error pulse train are in a low state;

loading a current value of said first integral clock CI 1 into a second integral clock C 12 each time said first integral clock CI 1 transitions from a high state to a low state;

counting down from said loaded current value with said second integral clock CI 2 at a frequency fI 2 until a zero value is reached; and

determining an integral error tern representing a time average of a signal which is held high while said second integral clock CI 2 is in a high state and held low while said second integral clock CI 2 is in a zero state, said control signal being dependent upon said integral error term; and

providing said control signal as an input to said target system.

6. A method of regulating a target system, comprising the steps of:

providing a reference signal;

generating a plurality of digital signals defining a reference pulse train with a frequency dependent upon said reference signal;

providing a target system to be regulated, said target system having an output in the form of a plurality of digital signals defining a feedback pulse train having a frequency;

comparing said frequency of said reference pulse train wit said frequency of said feedback pulse train, and substantially aligning a leading edge of each digital signal in said reference pulse train with a leading edge of each digital signal in said feedback pulse train;

generating a control signal dependent upon said comparison without regard to phase locking said feedback pulse train to said reference signal, said generating step including the substeps of:

generating a proportional error pulse train including a plurality of digital signals, each said digital signal representing an error between a corresponding pair of aligned digital signals of said reference pulse train and said feedback pulse train;

counting up from zero with a first derivative clock CD 1 at a frequency fD 1 when said digital signals of said proportional error pulse train are in a high state;

subtracting a current state of said first derivative clock CD 1 from a current state of a register R each time said first derivative clock CD 1 transitions from a high state to a low state;

loading said subtracted state into a second derivative clock CD 2 ;

loading said current state of said first derivative clock CD 1 into said register R;

resetting said first derivative clock CD 1 to zero;

counting down with said second derivative clock CD 2 at a frequency fD 2 after said subtracted state is loaded therein;

maintaining said first integral clock CI 1 at a current value when said digital signals of said proportional error pulse train are in a low state; and

determining a derivative error term representing a time average of a signal which is held high while said second derivative clock CD 2 is in a high state and held low while said second derivative clock CD 2 is in a zero state, said control signal being dependent upon said derivative error term; and

providing said control signal as an input to said target system.

7. A method of regulating a target system, comprising the steps of:

providing a reference signal;

generating a plurality of digital signals defining a reference pulse train with a frequency dependent upon said reference signal;

providing a target system to be regulated, said target system having an output in the form of a plurality of digital signals defining a feedback pulse train having frequency, said frequency of said feedback pulse train varying with time;

comparing said frequency of said reference pulse train with said frequency of said feedback pulse train;

generating a control signal dependent upon said comparison without regard to phase locking said feedback pulse train to said reference signal; and

providing said control signal as an input to said target system.