Controlling two monitors with transmission of display data using a fifo buffer

1. A method for controlling two monitors on the basis of an input-side pixel data stream, in which pixels for a line are arranged serially, wherein one part of each line of the input-side pixel data stream is displayed on one monitor and another part of the line is displayed on another monitor, comprising the following steps:

storing one part of the line of the input-side pixel data stream in one FIFO memory device without previous buffering;

subsequent to the storing of the first part, storing the other part of the line of the input-side pixel data stream in another FIFO memory device without previous buffering;

reading out one FIFO memory device with the pixel frequency with which one monitor is operated; and

reading out the other FIFO memory device with its pixel frequency with which the other monitor is operated.

2. A method according to claim 1 , with the following additional step:

creating timing control signals for controlling the monitors on the basis of timing control signals of the input-side pixel data stream.

3. A method according to claim 1 , with the following additional step:

delaying timing control signals of the input-side pixel data stream, whereby one of the monitors is controlled with a time delay and in synchronism with the other monitor.

4. A method according to claim 1 ,

wherein one part of each line of the input-side pixel data stream and the other part of each line of the input-side pixel data stream are of the same size and together have the length of a line of the input-side pixel data stream.

5. A method according to claim 4 , having the following additional steps:

setting a counter reference value to the number of pixels of one part of each line of the input-side pixel data stream; and

counting the pixels of each line of the input-side pixel data stream by counting the pulses of a clock with which the input-side pixel data stream is stored in each of the FIFO memory devices.

6. A method according to claim 5 , with the following additional steps:

enabling the storage of one part of the line of the input-side pixel data stream in one FIFO memory device and blocking storage in the other FIFO memory device before reaching the counter reference value and after the appearance of a blanking signal; and

enabling the storage of the other part of the line of the input-side pixel data stream in one FIFO memory device and blocking storage in the other FIFO memory device after reaching the counter reference value and after the appearance of the blanking signal.

7. A method according to claim 6 , with the following additional steps:

setting the pixel frequency of each monitor to half the clock frequency;

halving the frequency of the clock signal;

reading out one FIFO memory device with the halved clock frequency on appearance of the blanking signal;

delaying the blanking signal by a time which is equal to the number of pixels of one part of the line of the input-side pixel data stream multiplied by the period duration of the clock signal; and

reading out the other FIFO memory device on appearance of the delayed blanking signal in such a way that both FIFO memory devices are read out in synchronism and with a time shift.

8. A method according to claim 4 , with the following additional steps:

detecting a horizontal synchronization signal in the input-side pixel data stream;

delaying the horizontal synchronization signal by a time which is equal to the number of pixels of one part of the line of the input-side pixel data stream multiplied by the period duration of the clock signal; and

reading out the other FIFO memory device after the appearance of the delayed horizontal synchronization signal in such a way that both FIFO memory devices are read out in synchronism and with a time shift.

9. A method according to claim 1 ,

wherein the pixel frequency with which on monitor is operated and the pixel frequency with which the other monitor is operated together amount to the clock frequency with which one part of the line of the input-side pixel data stream is stored in one FIFO memory device and the other part of the line of the input-side pixel data stream is stored in the second FIFO memory device.

10. A monitor control circuit for controlling two monitors on the basis of an input-side pixel data stream, in which pixels for a line are arranged serially, wherein one part of each line of the input-side pixel data stream is displayed on one monitor and another part of the line of the input-side pixel data stream is displayed on another monitor, comprising:

two FIFO memory devices; and

a control device for controlling the storage of one part of the line of the input-side pixel data stream in one FIFO memory device without previous buffering, for controlling the storage of the other part of the line of the input-side pixel data stream in the other FIFO memory device without previous buffering and subsequent to the storing of the first part, for controlling the readout of one FIFO memory device with the pixel frequency with which one monitor is operated, and for controlling the readout of the other FIFO memory device with the pixel frequency with which the other monitor is operated.

11. A monitor control circuit according to claim 10 ,

wherein the control includes a time generator which creates timing control signals for controlling the monitors on the basis of timing control signals of the input-side pixel data stream and which is also connected to a frequency setting device for setting the pixel frequencies with which the monitors are operated so as to take account of the pixel frequency of the input-side pixel data stream.

12. A monitor control circuit according to claim 11 ,

wherein the control also includes a FIFO control logic, the FIFO control logic comprising:

a screen resolution register, which can be connected to a host bus of a computer and which supplies length values of one part and of the other part of the line of the input-side pixel data stream in response to control signals from the computer;

a pixel counter, which can be connected to the time generator and which creates FIFO control signals for controlling the two FIFO memory devices on the basis of the timing control signals of the input-side pixel data stream; and

a programmable delay unit, which creates delayed control signals for controlling one of the monitors on the basis of timing control signals and on the basis of the lengths of the two parts of the line of the input-side pixel data stream.