Memory architecture for a multiple format video signal processor
View Patent ↗A video decoder transcodes video data from various input formats to a predetermined output format. Input data may be standard definition data or MPEG2 compressed data. Standard definition data are rearranged into block format to be compatible with the decoder's single display processor. The display processor selectively processes and conveys either MPEG2 format data or non-MPEG2 format data to a display device. A block based frame memory stores MPEG2 and non-MPEG2 pixel block data, as well as standard definition data in raster line format during processing.
1. A digital processor having common architecture for processing multiple format video signals, comprising:
an input network for receiving high definition formatted video data and standard definition formatted video data;
a decoder coupled to said input network for producing high definition decoded and decompressed data;
a converter coupled to said input network for converting said standard definition formatted data to a format compatible with said high definition formatted data;
a common memory for storing high definition and standard definition formatted data during processing by said processor; and
a display processor for processing said high definition formatted data and said converted standard definition formatted data for display.
2. The processor of claim 1 , wherein:
said decoded and decompressed high definition data is in a block format;
said high definition data is MPEG2 compatible;
said display processor accepts video data in a block format; and
said converter converts said standard definition data to block format.
3. The processor of claim 1 , wherein:
said input network receives burst compressed data.
4. The processor of claim 1 , wherein:
said memory receives block-based data, and field and fame data in raster format.
5. The processor of claim 2 , further comprising:
a recompressor for recompressing said decoded and decompressed MPEG2 data prior to storage in said memory.
6. The processor of claim 1 , wherein:
said display processor is programmable to provide an output video data format compatible with a display device coupled to said display processor.
7. The processor of claim 1 , wherein
said input network includes an input for receiving MPEG2 format data and an input for receiving non-MPEG2 format data;
said display processor includes a block-to-line converter for processing block format MPEG2 data and line-to-block converted non-MPEG2 format data; and
said common memory stores said MPEG2 format data and said non-MPEG2 format data during processing by said system.
8. The system of claim 7 ; wherein:
said memory receives block-based data, and field and frame data in raster format.
9. The processor of claim 1 , comprising
a first processing path, associated with said input network, comprising an input for receiving MPEG2 format information, an MPEG2 decoder corresponding to said decoder, and said display processor having an output for conveying image information to a display device;
a second processing path, associated with said input network, comprising an input for receiving standard definition format information, a line-to-block converter and said display processor;
switching means for selectively conveying display information to said display output via said first and said second processing paths; and wherein
said common memory is block based and is coupled to said first and said second processing paths;
said display processor includes means for changing the resolution of said standard definition format information; and
said switching means stores said standard definition format information in said memory during processing.
10. A system according to claim 9 , wherein:
said memory receives block-based data, and field and frame data in raster format.
11. A method for processing multiple format video signals, comprising the steps of:
receiving a signal comprising data to be processed
identifying said received signal as one of MPEG2 format signal and standard definition format signal
decoding input MPEG2 format signal to produce block format data when received
pre-processing input standard definition format signal to produce block format data when received
conditioning said conveyed data to a format suitable for display
storing said MPEG2 format data and said standard definition format data in a common memory during processing; and
conveying display conditioned data to a display device.
12. A method according to claim 11 , wherein:
said pre-processing step converts line format data or block format data.
13. A method according to claim 11 , wherein:
said conditioning step converts block format data to line format data.
14. A method according to claim 11 , wherein:
said memory receives block-based data, and field and frame data in raster format.