Monolithic payload IF switch
View Patent ↗A crosspoint switch architecture ( 10 ). The inventive architecture ( 10 ) includes a monolithic substrate ( 11 ) on which a plurality (N) of electrical inputs are provided. In addition, a plurality (M) of electrical outputs are provided on the substrate ( 11 ). A switch is disposed on the substrate ( 11 ) for selectively interconnecting the inputs to the outputs and a control circuit ( 16 ) is disposed on the substrate ( 11 ) for controlling the switch. The switch comprises M, N to 1 , multiplexers ( 14 ), each multiplexer ( 14 ) being adapted to receive each of the N electrical inputs. In the illustrative embodiment, each of the N inputs to each of the multiplexers is received through a respective one of N switchable amplifiers ( 18 ). The output of each amplifier ( 18 ) is provided to a respective one of N switchable isolation buffers ( 19 ). The outputs of the buffers ( 19 ) are summed and buffered to provide the output of each multiplexer ( 14 ). The control circuit ( 16 ) selects which input is to be passed through to the output of a given multiplexer ( 14 ). In the illustrative embodiment, the control circuit ( 16 ) includes a serial in, parallel out shift register and decode logic circuitry.
1. A crosspoint switch architecture having:
a monolithic substrate;
a plurality (N) of electrical inputs provided on said substrate;
a plurality (M) of electrical outputs provided on said substrate;
switch means disposed on said substrate for selectively interconnecting said inputs to said outputs, said switch means having M multiplexers and a plurality (N) switchable amplifiers, each of said switchable amplifier operatively coupled to a corresponding one of said N inputs; and
means disposed on said substrate for controlling said switch means,
wherein each multiplexer includes N selection multiplexers,
wherein each of said N inputs to each of said multiplexer is received through a respective one of said N switchable amplifiers, and
wherein one of the N inputs can be selected for outputting to one of the M outputs by switching on the corresponding switchable amplifiers and disabling the rest of the switchable amplifiers.
2. The invention of claim 1 , wherein the Switch means further comprise a plurality (N) of isolation buffers, each of said isolation buffers operatively coupled to the output of a corresponding one of switchable amplifiers.
3. The invention of claim 1 wherein said control means includes a serial in, parallel out shift register.
4. A crosspoint switch architecture having:
a monolithic substrate;
a plurality (N) of electrical inputs provided on said substrate;
a plurality (M) of electrical outputs provided on said substrate;
switch means disposed on said substrate for selectively interconnecting said inputs to said outputs, said switch means having M multiplexers; and
means disposed on said substrate for controlling said switch means,
wherein each multiplexer includes N selection multiplexers.
5. The invention of claim 4 further including means for summing the outputs of said N selection multiplexers to provide a single output.
6. The invention of claim 5 further including means for buffering said single output.
7. A crosspoint switch architecture having:
a monolithic substrate;
a plurality (N) of electrical inputs provided on said substrate;
a plurality (M) of electrical outputs provided on said substrate;
switch means disposed on said substrate for selectively interconnecting said plurality of electrical inputs to said plurality of electrical outputs, said switch means having M multiplexers; and
means disposed on said substrate for controlling said switch means
wherein each multiplexer includes N selection multiplexers, and
wherein each of said N inputs to each of said N selection multiplexers is received through a respective one of N switchable isolation buffers.
8. The invention of claim 7 further including means for buffering said single output.
9. A crosspoint switch architecture having:
a monolithic substrate;
a plurality (N) of electrical inputs provided on said substrate;
a plurality (M) of electrical outputs provided on said substrate;
M multiplexers disposed on said substrate for selectively interconnecting said plurality of electrical inputs to said plurality of electrical outputs, each of said multiplexers being an N to 1 multiplexer, whereby each multiplexer is adapted to receive each of said plurality of electrical inputs; and
a serial in, parallel out shift register disposed on said substrate for controlling said multiplexers,
wherein each multiplexer includes N selection multiplexers.
10. The invention of claim 9 further including means for buffering said single output.